> Am 03.10.2023 um 03:32 schrieb J. Gareth Moreton via fpc-devel > <fpc-devel@lists.freepascal.org>: > > Hi everyone, > > This is mainly to Florian, but also to anyone else who can answer the > question - at which point did a complex LEA instruction (using all three > input operands and some other specific circumstances) get slow?
Maybe check Agner’s list? > Preliminary research suggests the 486 was when it gained extra latency, and > then Sandy Bridge when it got particularly bad. Icy Lake seems to be the > architecture where faster LEA instructions are reintroduced, but I'm not sure > about AMD processors. > > Should I introduce a new x86 subprocessor named "ICYLAKE" or is there a > better name or does it fall under one of our categories already (CORE_AVX2 or > ZEN3)? If it doesn’t fit in the existing ones, you can always add new ones > > Kit > > _______________________________________________ > fpc-devel maillist - fpc-devel@lists.freepascal.org > https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
