On 5 Jan 2018, at 02:46, Jon Brawn <j...@brawn.org> wrote:
> This idea of Arm big.LITTLE systems having cache lines of different lengths
> really, really bothers me - how on earth is the cache coherency supposed to
> work in such a system? I doubt the usual cache coherency protocols would work
> - probably need a really MESSY protocol to deal with this config :-)
I believe that the systems that have different cache line sizes (which ARM
explicitly tells partners not to do) don’t allow cores from both the big and
little clusters to be active at the same time - the OS is supposed to migrate
everything entirely from one cluster to the other. The more complex designs,
that allow mixes of cores from two or three different clusters that I’m aware
of all have the same cache line size.
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