On Fri, Feb 09, 2001 at 11:00:04AM +1100, Peter Jeremy wrote:
> On 2001-Feb-08 22:21:32 +0100, Bernd Walter <[EMAIL PROTECTED]> wrote:
> >On sparcv8 you don't have an operation doing conditionaly stores and
> >you don't have RMW operations.
> >The only way to do is to have a global lock variable on which you spin
> >until the current client finishes.
> The SPARC architecture supports SMP so there must be some
> synchronisation primitive that works between processors (disabling
> interrupts only works on the current processor).  Normally the same
> primitive can be used to synchronise accesses within the same
> processor.  I know the older SPARC's had a test-and-set instruction
> which was locked RMW - there must be something similar in v8 and v9.

sparcv8 has:
LDSTUB - which is a atomic load into register and store 0xff
SWAP - which exchanges a register with memory atomicly

sparcv9 has additionaly the Comapare And Set (CAS) operation which makes
it similar in use as alpha.

I can't speak for sparcv7 and older but maybe you are refering to
sparcv9 with it's CAS operation as an "older" SPARC or have a vendor
specific extension in mind.

Disabling interrupts will work fine because the reason is to avoid
deadlocks. The only thing needed is that the processor holding the lock
can't be interrupted until it's finished.
If another CPU want's the same lock it can spinwait because the other
CPU still gets the chance to release the lock.

No doubt the available primitives are enough - but I wanted to know
if its neccessary to go the complete ugly way.

The sparv8 way for FreeBSDs atomic_ is now clear to me:
disable ints for the CPU in question
fetch the lock
do the real work
restore ints

Thank you all for making this clear.

B.Walter              COSMO-Project         http://www.cosmo-project.de
[EMAIL PROTECTED]         Usergroup           [EMAIL PROTECTED]

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