On Fri, 12 Mar 2010 15:13:34 -0800
Weongyo Jeong <weongyo.je...@gmail.com> wrote:

> I thought that your opinion was right and if mem is
> 0xf4000000-0xf4003fff (16 Kb) I thought the device has 4 cores.  However
> it looks this was wrong according to the below document:
>       http://voodoowarez.com/bcm5365p.pdf
> Please see Section 3: PCI Core, PCI Bus (Page 34) that it indicates that
> 16Kb, maybe 8 Kb in the old devices is core register region.
>   "Accesses to the lower half of the core register region are translated
>    into system backplane accesses using the PCIBAR0Window register"
>   "Accesses to offsets 0x1000 to 0x17FF of this region initiate a direct
>    access to the external SPROM"
> If we just access memory using offset + core and bus_space_read_x
> interfaces it would actually not access core register region.
> So without solving this problem it looks it could not remove coreswitch
> routines.
> regards,
> Weongyo Jeong


this document about SoC BCM5365P, not about PCI device with PCI to SSB bridge.
I know in SoC`s like BSM5365 (I test it in BCM5354 and BCM5836) core switching 
is not required.

BCM5354 - http://lists.freebsd.org/pipermail/freebsd-mips/2009-June/000421.html
BCM5836 - 

With PCI device, when device report memory window 0xf4000000-0xf4003fff, why we 
can`t use full window?

May be You can test your code without core switching?

Alex RAY <r...@ddteam.net>
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