Hi,
I've been contacted by Marco Trillo and I think he has found the
source of the SMP problem.
The problem seems to rely on Intel ICH7. Basically we need to disable
the "LEGACY_USB" bit before we calibrate the clocks.
"LEGACY_USB", according to Marco (I don't have the ICH7 spec at hand),
"causes legacy USB circuit to generate SMIs".
Please try the following patch:
--- sys/amd64/isa/clock.c.orig 2007-11-04 20:31:09.000000000 +0000
+++ sys/amd64/isa/clock.c 2007-11-04 20:34:59.000000000 +0000
@@ -577,6 +577,8 @@ startrtclock()
writertc(RTC_STATUSA, rtc_statusa);
writertc(RTC_STATUSB, RTCSB_24HR);
+ outl(0x430, inl(0x430) & ~0x8);
+
freq = calibrate_clocks();
#ifdef CLK_CALIBRATION_LOOP
if (bootverbose) {
--- sys/i386/isa/clock.c.orig 2007-11-04 20:34:03.000000000 +0000
+++ sys/i386/isa/clock.c 2007-11-04 20:34:30.000000000 +0000
@@ -621,6 +621,8 @@ startrtclock()
writertc(RTC_STATUSA, rtc_statusa);
writertc(RTC_STATUSB, RTCSB_24HR);
+ outl(0x430, inl(0x430) & ~0x8);
+
freq = calibrate_clocks();
#ifdef CLK_CALIBRATION_LOOP
if (bootverbose) {
This should probably fix two issues:
1) The second core should start without any trick (e.g. key press)
2) We should be able to run with HZ=1000 (the default) without any
problem. To check if this is indeed the case, try booting with HZ=1000
(loader.conf variable kern.hz) and check if your CPU clock shows up
correctly in the dmesg. After that, please also check if 'time sleep
1' takes one second (not more and not less).
Also, please test if there are any USB problems.
Note: this is still a hack. I'm still thinking about a way to
correctly identify on which systems we need to apply this fix.
Regards.
--
Rui Paulo
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