On Tue, 18 Dec 2012 09:22:22 +0100
Hans Petter Selasky <hsela...@c2i.net> wrote:
> On Tuesday 18 December 2012 08:49:31 Andrew Turner wrote:
> > Hello,
> > Oleksandr and myself have been looking into why when we enable the
> > write-back cache on the PandaBoard there are kernel panics with
> > USB. We have tracked it down to an issue appending the ehci_qh_t to
> > the list at the end of ehci_setup_standard_chain().
> > I have a patch at  that allows me to run sha256 on a 40MB file
> > over NSF using the built in smsc USB ethernet chip. The problem is
> > I have had to place a call to DELAY before EHCI_APPEND_QH. This is
> > obviously not the correct solution.
> > Is anyone able to help me narrow down what is missing? It appears
> > to be a missing cache invalidate or flush somewhere but I haven't
> > been able to track down what cache function the DELAY is working
> > around.
> > Andrew
> >  http://fubar.geek.nz/files/freebsd/ehci_4.diff
> Can you dump the DMA tag belonging to the QH via and check wether it
> is mapped coherent or not. Thes QH- and TD- structures should not be
> cache mapped. Else cache has not been disabled on those pages.
The BUS_DMA_COHERENT flag does nothing on armv6 as we need the cache
enabled for atomic operations to work correctly and we would have to
disable the cache on the entire page. This is acceptable behaviour from
the description of the flag in the busdma man page.
Is there a reason the QH and TD structures shouldn't be cache mapped?
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