Add an interface to trigger the remote processor to reinitialize the GPU
zap shader on power-up.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
 drivers/firmware/qcom_scm-32.c |  5 +++++
 drivers/firmware/qcom_scm-64.c | 15 +++++++++++++++
 drivers/firmware/qcom_scm.c    |  6 ++++++
 drivers/firmware/qcom_scm.h    |  2 ++
 include/linux/qcom_scm.h       |  2 ++
 5 files changed, 30 insertions(+)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index c6aeedb..1a0876c 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -560,3 +560,8 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
 
        return ret ? : le32_to_cpu(out);
 }
+
+int __qcom_scm_gpu_zap_resume(struct device *dev)
+{
+       return -ENOTSUPP;
+}
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 4a0f5ea..31089c1a 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -358,3 +358,18 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool 
reset)
 
        return ret ? : res.a1;
 }
+
+int __qcom_scm_gpu_zap_resume(struct device *dev)
+{
+       struct qcom_scm_desc desc = {0};
+       struct arm_smccc_res res;
+       int ret;
+
+       desc.args[0] = 0;
+       desc.args[1] = 13;
+       desc.arginfo = QCOM_SCM_ARGS(2);
+
+       ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, 0x0A, &desc, &res);
+
+       return ret ? : res.a1;
+}
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index e64a501..4912a92 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -308,6 +308,12 @@ static const struct reset_control_ops 
qcom_scm_pas_reset_ops = {
        .deassert = qcom_scm_pas_reset_deassert,
 };
 
+int qcom_scm_gpu_zap_resume(void)
+{
+       return __qcom_scm_gpu_zap_resume(__scm->dev);
+}
+EXPORT_SYMBOL(qcom_scm_gpu_zap_resume);
+
 /**
  * qcom_scm_is_available() - Checks if SCM is available
  */
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index 3584b00..581f934 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -56,6 +56,8 @@ extern int  __qcom_scm_pas_auth_and_reset(struct device *dev, 
u32 peripheral);
 extern int  __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
 extern int  __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
 
+extern int __qcom_scm_gpu_zap_resume(struct device *dev);
+
 /* common error codes */
 #define QCOM_SCM_V2_EBUSY      -12
 #define QCOM_SCM_ENOMEM                -5
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index cc32ab8..e1729fb 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -37,6 +37,8 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t 
addr,
 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
 extern int qcom_scm_pas_shutdown(u32 peripheral);
 
+extern int qcom_scm_gpu_zap_resume(void);
+
 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON    0x0
 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF   0x1
 
-- 
1.9.1

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