The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.

In order to switch out of secure mode the GPU executes a special
shader that clears out the GMEM and other sensitve registers and
then writes a register. Because the kernel can't be trusted the
shader binary is signed and verified and programmed by the
secure world. To do this we need to read the MDT header and the
segments from the firmware location and put them in memory and
present them for approval.

For targets without secure support there is an out: if the
secure world doesn't support secure then there are no hardware
protections and we can freely write the SECVID_TRUST register from
the CPU. We don't have 100% confidence that we can query the
secure capabilities at run time but we have enough calls that
need to go right to give us some confidence that we're at least doing
something useful.

Of course if we guess wrong you trigger a permissions violation
which usually ends up in a system crash but thats a problem
that shows up immediately.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 20 ++++++++++
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++++++++++++++++++++++++++++++++++-
 2 files changed, 90 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index f71b468..bb9f418 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -133,6 +133,18 @@
                method = "smc";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               peripheral_reserved: peripheral_region@8ea00000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0 0x8ea00000 0 0x2b00000>;
+                       no-map;
+               };
+       };
+
        soc: soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -543,6 +555,14 @@
                                        qcom,gpu-freq = <27000000>;
                                };
                        };
+
+                       qcom,zap-shader {
+                               compatible = "qcom,zap-shader";
+                               memory-region = <&peripheral_reserved>;
+
+                               qcom,firmware = "a530_zap";
+                               qcom,pas-id = <13>;
+                       };
                };
 
                mdp_smmu: arm,smmu@d00000 {
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index c4a9a12..6cf9429 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -469,6 +469,55 @@ static int a5xx_ucode_init(struct msm_gpu *gpu)
        return 0;
 }
 
+static int a5xx_zap_shader_resume(struct msm_gpu *gpu)
+{
+       int ret;
+
+       ret = qcom_scm_gpu_zap_resume();
+       if (ret)
+               DRM_ERROR("%s: zap-shader resume failed: %d\n",
+                       gpu->name, ret);
+
+       return ret;
+}
+
+static int a5xx_zap_shader_init(struct msm_gpu *gpu)
+{
+       static bool loaded;
+       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+       struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
+       struct platform_device *pdev = a5xx_gpu->pdev;
+       struct device_node *node;
+       int ret;
+
+       /*
+        * If the zap shader is already loaded into memory we just need to kick
+        * the remote processor to reinitialize it
+        */
+       if (loaded)
+               return a5xx_zap_shader_resume(gpu);
+
+       /* Populate the sub-nodes if they haven't already been done */
+       of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+
+       /* Find the sub-node for the zap shader */
+       node = of_find_node_by_name(pdev->dev.of_node, "qcom,zap-shader");
+       if (!node) {
+               DRM_ERROR("%s: qcom,zap-shader not found in device tree\n",
+                       gpu->name);
+               return -ENODEV;
+       }
+
+       ret = _pil_tz_load_image(of_find_device_by_node(node));
+       if (ret)
+               DRM_ERROR("%s: Unable to load the zap shader\n",
+                       gpu->name);
+
+       loaded = !ret;
+
+       return ret;
+}
+
 #define A5XX_INT_MASK (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \
          A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \
          A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \
@@ -653,8 +702,27 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
                        return -EINVAL;
        }
 
-       /* Put the GPU into unsecure mode */
-       gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
+       /*
+        * Try to load a zap shader into the secure world. If successful
+        * we can use the CP to switch out of secure mode. If not then we
+        * have no resource but to try to switch ourselves out manually. If we
+        * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
+        * be blocked and a permissions violation will soon follow.
+        */
+       ret = a5xx_zap_shader_init(gpu);
+       if (!ret) {
+               OUT_PKT7(gpu->rb, CP_SET_SECURE_MODE, 1);
+               OUT_RING(gpu->rb, 0x00000000);
+
+               gpu->funcs->flush(gpu);
+               if (!gpu->funcs->idle(gpu))
+                       return -EINVAL;
+       } else {
+               /* Print a warning so if we die, we know why */
+               dev_warn_once(gpu->dev->dev,
+                       "Zap shader not enabled - using SECVID_TRUST_CNTL 
instead\n");
+               gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
+       }
 
        return 0;
 }
-- 
1.9.1

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