On 5/14/2026 6:13 PM, Konrad Dybcio wrote: > On 5/12/26 12:23 AM, Akhil P Oommen wrote: >> Adreno 840 present in Kaanapali SoC is the second generation GPU in >> A8x family. It is based on the new slice architecture with 3 slices, >> higher GMEM/caches etc. >> >> There is some re-arrangement in the reglist to properly cover maximum >> register region. Other than this, the DT description is mostly similar >> to the existing chipsets except the OPP tables. >> >> Signed-off-by: Akhil P Oommen <[email protected]> >> --- > > [...] > >> + gpu_opp_table: opp-table { >> + compatible = "operating-points-v2-adreno", >> + "operating-points-v2"; >> + >> + opp-222000000 { >> + opp-hz = /bits/ 64 <222000000>; >> + opp-level = >> <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; >> + opp-peak-kBps = <2136718>; >> + opp-supported-hw = <0x0f>; >> + /* ACD is disabled */ >> + }; > > The clock plan also has a 160 MHz OPP @ LOWSVS_D3 and there's a couple of > interim OPPs that you have that aren't part of it (but maybe you have > better docs)
I somehow assumed that the 160Mhz was a thermal-only corner. Seems it is not. Let me revisit the OPP table again. Yeah, the doc is outdated. Looks like there was some last minute updates to the OPP table. Also, we should update a6xx_hfi.h to accommodate more than 16 GX levels. -Akhil. > > Otherwise lgtm but the size of the GPU region and the GMU base look > slightly confusing when I'm comparing them against the reg map > > Konrad
