On Sun, Dec 21, 2014 at 12:05 AM, glen english <g...@cortexrf.com.au> wrote:
> Easy when you've got a 70K logic cell FPGA, but still possible on
> STM32-4, I think you need to come up with a clever way to run the demod

Well keep in mind that there can be multiple target demodulators for
this.  If a modulation scheme is competitive on a small STM32-4 with
the most highly performing scheme you could use with a demod in those
constraints it would also be good someone who happens to have 70k LU
on an fpga to throw at it (or many fast x86_64 cores) could
potentially get a few more dB of low SNR performance.

Having a "scalable" setup where people who have huge amounts of money
to blow getting small improves can get small improvements-- e.g. by
concurrently demodulating with many choices of timing offset and
equalizer parmeters and running a big dynamic programming solution
over all the error correcting, timing, equalizer, all regularized by
stronger statistical speech models than used in the codec, etc..
would serve VHF digital well, because it would allow people with that
optimization bug to chase it as far as they want, an would encourage
them to get more people producing these signals that their fancy
hardware could consume. And if this scaling can be accomplished
primarily by adding more commodity cpu power and software (after
you've gotten past the initial SDR input), it doesn't require quite
the amount of cost ineffective special purpose stuff.


(I sort of boggle that people will spend thousands of dollars for
fancy radios which are only sold in fairly small quantities and so are
fairly expensive for what they deliver,  but a modern ham shack does
not usually have a half rack of 8 core processors or an FPGA array
doing DSP... the returns are diminishing, sure, but cpu power is cheap
compared to specialized radio hardware)

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