The CPU load is proportional to the initial freq offset estimation 
bandwidth.  I'm inclined to wait a little and see if this is a real problem.


On 15/09/15 13:00, Bruce Perens wrote:
> How difficult would it be to widen your software PLL? That might make
> the rest moot.
>
> On Mon, Sep 14, 2015 at 8:06 PM, David Rowe <[email protected]
> <mailto:[email protected]>> wrote:
>
>     Yes I'll add some "sights" to the graticule some time.  An additional
>     complication is that the 700B carrier spacing is non-uniform, a little
>     trick to reduce PAPR.
>
>     - David
>
>     On 15/09/15 10:47, Peter Reichelt wrote:
>      > David and list
>      > As tuning is more critical on the 700 mode as compared to the
>     1600 mode and there is an absence of a distinct central carrier then
>     a couple of extra tick marks on the FreedDV GUI showing the edges of
>     the signal, when correctly tuned, as well as the centre would
>     provide easier tuning of signals using coherent psk modes. Note this
>     is compounded by having an even numbers of carriers where correct
>     tuning is with the centre tick mark between the 7th and 8th
>     carriers,not aligned with a carrier. It is easy to select the mid
>     point between the wrong carrier pair.
>      > regards
>      > Peter VK5APR
>      >
>      >
>     
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