Hi Glen, Codec 2 runs well on small floating point uCs, so not much to be gained there in a FPGA implementation. A few years ago Danilo did some fine work on making it run faster on the stm32 but that's been the last real effort. It's probably fast enough.
Most of the LPCNet CPU load is in some simple matrix operations ... 16000 times a second using 1.2E6 floating point weights. It's all recursive so single core, So you'd meed memory for them. I suspect a SIMD fixed point implementation would be a better move than FPGA, and get it to the point where it runs on many more CPUs. It may run on a Pi4 if someone wants to make some more optimisation happen. If you really want to play FPGA, maybe something like a Zync/Pluto based HT, with all the filtering, modest PA etc. Something that the average Ham can click together to run open source radio. Right now I'm having fun with HF and VHF data using the Codec 2 modems, and one day I will have another lap around Codec 2 quality in the 600 bit/s range and a new FreeDV "mode" absorbing lessons learned the past few years. Speech quality still needs some work, and there's a few more dB to get gained with some waveform improvements. For the C++/Gui/sound card inclined, freedv-gui needs some love (see issues list). Cheers, David On 22/6/20 10:45 am, glen english wrote: > Hi Jeroen , David > > I'm interested in assisting where I can in the whole freeDV sphere. I've > recently gone over the last year of forum posts to see what I have > missed in detail. > > I'd like to be able to implement LPC122, 203 (and Codec2) on a small , > cheap FPGA for use with FreeDV . > > I am not sure if this discussion needs a separate forum. Please let me > know. > > I'm going to take a look at the code and understand how suited to a > processor or an FPGA from a cost/power point of view. I am a XIlinx user > , and I am also a XIlinx Alliance Partner, so I get access to cool stuff. > > As you know, complex algorithms are generally best executed (and more > quickly programmed and debugged) on a processor, until you run out of > speed or power, at which the programmer gradually hands over more and > more of the work to an FPGA co processor. > > 3 to 6 GFLOPS is of course no space for an STM32. But might be good as > a FPGA co processor for an STM32, to execute both CODEC2 and LPCNET and > take the heavy lifting out of the STM32 and turn the codec job into a > SPI peripheral. > > I am thinking a medium Spartan7 (maybe $10-$20) or a small ZYNQ (single > core Cortex A9 and a heap of FPGA fabric $20-$30) > > Smartphone cores are good, but running flat out for more than a few > seconds they (can) burn up . Sure they decode video, but that's on > dedicated hard blocks. > > let me know what you think. > > Another thing- Jeroen, if you would like me to organise a XIlinx U50 > card to the task, I think my personal finances could stretch that. (or > I could head down that road to make things fast to develop) > > https://www.xilinx.com/publications/product-briefs/alveo-u50-product-brief-v2.pdf > > > https://www.xilinx.com/support/documentation/data_sheets/ds965-u50.pdf > > https://www.xilinx.com/products/boards-and-kits/alveo/u50.html > > Xilinx have wrapped an easy to use framework around it. That's not the > sort of FPGA I am proposing, but it is a useful method of running up > testing with great speed. The FPGA has 8 GBytes of essentially 1024 bit > wide full core speed memory....a 10k$ FPGA. > > 73 > > > > > > _______________________________________________ > Freetel-codec2 mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/freetel-codec2 _______________________________________________ Freetel-codec2 mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/freetel-codec2
