Hi Glenn, Having just become the owner of an ADALM Pluto, which also has an (albeit small) Xilinx FPGA on board, I'm very interested in this.
I've only just begun dipping my toe into the ecosystem, so I'm not expecting that I'll be able to contribute immediately to these efforts (my hello-world for the Pluto was an update to dimp1090), but compiling the Analogue Devices supplied FPGA image is two steps away on my roadmap (after compiling the OS). When I'm not playing with amateur radio, I'm a software engineer. de Onno VK6FLAB -- finger painting on glass is an inexact art - apologies for any errors in this scra^Hibble ()/)/)() ..ASCII for Onno.. On Mon., 22 Jun. 2020, 10:57 glen english, <[email protected]> wrote: > Hi Don > > There is MUCH documentation on using the FPGA fabric for RNNs. > > > https://www.xilinx.com/support/documentation/application_notes/xapp1332-neural-networks.pdf > > There are a couple of options and the FP options is easily synthesised. > > The xilinx native DSP block DSP48E1 multiplier/adder size in 7 series > (mature) is (25bit x 18bbit) + 18b + 48b with 48 bit + carryout > accumulator, and they are designed to cascade for all manner of bit > sizes.. Up to whatever you can dream of (usually a column height ) IE > the fabric knows that you might extend them madly. > > That is you could run large precision integer. There is a truncation, > barrel shifting and symmetric rounding function in the DSP block > (pipelined, 400 MHz sustained throughput) . Multipliers are cheap these > days. 80 x DSP48E1 blocks at 400 MHz in a $15 FPGA. > > For floating point in fabric, one solution is to use a FP component . > > The full range of IEEE functions are available . addsub,divide, recip, > exp, log, mul, recip-sqrt , abs, mul-acc, and the implemenation can be > fully pipelined for 350 MHz throughput in slow devices. > > Precision is arbrirary- exponent and mantissa width from 0 to 64 bits. > > Add/subtract : Example- consumes around 400 LUTs and runs at ~250 - > 400 MHz in slow parts, single precision, moderately pipelined. so > utilization is moderate, and of course, running them at 300 MHz you can > share the one around ... > > > glen > > On 6/22/2020 11:34 AM, Don wrote: > > One of the first steps in using an FPGA is often converting to integer > > math (it's all floats now). Just that might help with speed and memory. > > > > Don Reid > > > > On June 21, 2020 18:21:00 glen english <[email protected]> wrote: > > > >> Hi Jeroen , David > >> > >> I'm interested in assisting where I can in the whole freeDV sphere. I've > >> recently gone over the last year of forum posts to see what I have > >> missed in detail. > >> > >> I'd like to be able to implement LPC122, 203 (and Codec2) on a small , > >> cheap FPGA for use with FreeDV . > >> > >> I am not sure if this discussion needs a separate forum. Please let > >> me know. > >> > >> I'm going to take a look at the code and understand how suited to a > >> processor or an FPGA from a cost/power point of view. I am a XIlinx user > >> , and I am also a XIlinx Alliance Partner, so I get access to cool > >> stuff. > >> > >> As you know, complex algorithms are generally best executed (and more > >> quickly programmed and debugged) on a processor, until you run out of > >> speed or power, at which the programmer gradually hands over more and > >> more of the work to an FPGA co processor. > >> > >> 3 to 6 GFLOPS is of course no space for an STM32. But might be good as > >> a FPGA co processor for an STM32, to execute both CODEC2 and LPCNET and > >> take the heavy lifting out of the STM32 and turn the codec job into a > >> SPI peripheral. > >> > >> I am thinking a medium Spartan7 (maybe $10-$20) or a small ZYNQ (single > >> core Cortex A9 and a heap of FPGA fabric $20-$30) > >> > >> Smartphone cores are good, but running flat out for more than a few > >> seconds they (can) burn up . Sure they decode video, but that's on > >> dedicated hard blocks. > >> > >> let me know what you think. > >> > >> Another thing- Jeroen, if you would like me to organise a XIlinx U50 > >> card to the task, I think my personal finances could stretch that. (or > >> I could head down that road to make things fast to develop) > >> > >> > https://www.xilinx.com/publications/product-briefs/alveo-u50-product-brief-v2.pdf > >> > >> > >> https://www.xilinx.com/support/documentation/data_sheets/ds965-u50.pdf > >> > >> https://www.xilinx.com/products/boards-and-kits/alveo/u50.html > >> > >> Xilinx have wrapped an easy to use framework around it. That's not the > >> sort of FPGA I am proposing, but it is a useful method of running up > >> testing with great speed. The FPGA has 8 GBytes of essentially 1024 bit > >> wide full core speed memory....a 10k$ FPGA. > >> > >> 73 > >> > >> > >> > >> > >> > >> _______________________________________________ > >> Freetel-codec2 mailing list > >> [email protected] > >> https://lists.sourceforge.net/lists/listinfo/freetel-codec2 > > > > > > > -- > Glen English > RF Communications and Electronics Engineer > > CORTEX RF > & > Pacific Media Technologies Pty Ltd > > ABN 40 075 532 008 > > PO Box 5231 Lyneham ACT 2602, Australia. > au mobile : +61 (0)418 975077 > > > > _______________________________________________ > Freetel-codec2 mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/freetel-codec2 >
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