Josh
L4 has the FPU , it IS an Cortex M4 core.
but there are many many low power optimizations internally , with
respect to caching, memory bandwidth etc. Per is specificed at
1.25DMIPS/MHz for both F4 and L4. Some of the L4 low power facilities
are NOT available when running at performance of 1.25DMIPS/MHZ.
I think that you may want to reevaluate your strategy.
But, certainly it should compile and run and you would be able to
generate benchmarks for your implementation- that's really what you need
to do.
Exactly what power budget (milliwatts) do you have ?
do you need to encode real time ?
Glen English
STM32L0, L1, L2, F0 , F4, F7 and Xilinx FPGA person.
On 5/14/2021 8:51 AM, Josh Lloyd via Freetel-codec2 wrote:
Hi Bruce, thanks for your reply.
> Hardware floating point is requ
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