I think, based on my profressional experience with the F4 , L4, L, in
battery environments - you would be far better to use an F4 part for
this.
-aggressively down clock it when the full clock speed is unnecessary
You can save a ton of power doing that.
The chip is very good at changing clock speeds.
- you can disable cache, disable flash prefresh all saves heaps of power
- you can use a switched mode instead of LDO for the core if you really
need to. The core runs on 1.2V or down to 1.1V
that saves power.
- downclock peripherals, aggressively gate their clocks.
My opinion is that the ONLY reason to use an L4 for this is if up need
the thing to sleep doing NOTHING except waiting for an interrupt to wake
up.
The F4 will run on 1.8V. forget 3.3V . logic tralsate asd required. 1.8V
is the key to low power.
You might even use the F7 part and again, use the above methods to save
power. The F4 happily RUNS at 2mA power consumption when unbusy.
You can go to stop for 90% of the time and consume just 200uA average.
On 5/14/2021 1:04 PM, Josh Lloyd via Freetel-codec2 wrote:
Glen
> But, certainly it should compile and run and you would be able to
generate benchmarks for your implementation- that's really what you need
to do.
That's probably what I'll do, get an L4 and just test it, though knowing
roughly if it'll work before I go through the effort of shipping a
device is always a win in my opinion. I'm learning towards "it wont work
without effort" though.
> Exactly what power budget (milliwatts) do you have ?
I'm targeting less than 1 watt, probably around 500mW for the radio and
processor and other peripheral, and making use of low power sleep modes
to conserve energy in standby or while receiving.
> Do you need to encode real time ?
Some latency is tolerable, but the intent would be real time - yes.
Josh
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