The RADE paper has estimates of how much CPU is needed: https://arxiv.org/abs/2505.06671. Hope this helps!
-Mooneer K6AQ On Mon, Sep 21, 2026, 6:58 PM glen english LIST <[email protected]> wrote: > a while back, years now, I floated a "SM3000" project using FPGA +SoC > (integrated) hardware. > Then at about same time, LPCnet etc was the new kid on the block. > Suddenly, the horsepower required took a big hike. So, project went on > hold > > I have a bit more time up my sleeve, and substantial resources to make > this happen. I'm doing another priject right now that has a hard-burned in > CNN into the fpga fabric (no moving weights out of memory to the > transformers) (fpga reconfigures itself every few 100uS to adopt a > different function ) > > Target would be at least RADE. > But I am not in the loop enough to understand computational requirements. > If someone has time, they might converse with me here, or privately about > computational requirements. > It is also important to consider, that when there is an FPGA involved, > computational requirements of a software written task can be quite > different if parallel fpga resources can be thrown at something. IE mixed > implementation, which can save alot of power. And saving power means a much > simpler mechanical design, because designs that make lots of heat need more > advanced metalwork ideas to get rid of the heat . But that's a bit beyond > this discussoon. > > Such a design also needs plenty of capability in hand at Rev 1, because > fearyures and scope and capability requirementts always increase. > > -glen > > > On 22/09/2026 11:36, Ashhar Farhan wrote: > > We are assuming that with compression, the pa linearity holds. Which is > usually not the case. Advantage RADE > > _______________________________________________ > Freetel-codec2 mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/freetel-codec2 >
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