thanks Mooneer Yes, familiar with the paper,. with thanks
I'll need to sit down and write out (or use an LLM agent to do it) the individual computational steps.
The thing is, one needs to keep any FPGA hybrid implementation capable of being "scriptable" so that as the reference code changes, the hybrid FPHA/SoC code can be kept up to date without falling behind the PC code - IE - one click code generation. This is entirely feasible these days for the sort of thing we need. (IIE that isnt using every single flip flop on every single clock edge) .
regards On 22/09/2026 14:41, Mooneer Salem wrote:
The RADE paper has estimates of how much CPU is needed: https://arxiv.org/abs/2505.06671. Hope this helps!-Mooneer K6AQ
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