Daniel, thanks for your reply. I wasn't clear. It's not the PC that should
be getting this data, it is the FPGA attached to the EP6 slave FIFO. Since
it's just a FIFO it has no notion of NAK. For example, in the code below I
have set AUTOOUT=0. Now whenever an EP6 packet arrives from the host,
fifo_send() is invoked which rewrites the packet to a dummy set of bytes. I
tested this and it works. So far so good. But, crucially, if I invoke
fifo_send() on some_other_condition() e.g a button press, the FPGA sees
nothing on the FIFO. Is it just not possible to manually prod the slave
FIFOs like this? Or am I missing something?
// Called once at startup
//
void main_init(void) {
FIFOPINPOLAR = 0x03;
SYNCDELAY(); CPUCS = bmCLKSPD1; // 48MHz
SYNCDELAY(); IFCONFIG = (bmIFCLKSRC | bm3048MHZ | bmIFCLKOE |
bmSYNCFIFOS);
SYNCDELAY(); REVCTL = (bmDYN_OUT | bmENH_PKT);
SYNCDELAY(); EP6CFG = (bmVALID | bmBULK | bmDOUBLEBUFFERED);
SYNCDELAY(); FIFORESET = bmNAKALL;
SYNCDELAY(); FIFORESET = bmNAKALL | 6; // Reset EP6
SYNCDELAY(); FIFORESET = 0x00;
SYNCDELAY(); EP6FIFOCFG = 0x00;
SYNCDELAY(); OUTPKTEND = bmSKIP | 6;
SYNCDELAY(); OUTPKTEND = bmSKIP | 6;
sendCount = 0;
}
// Compose a packet to send on the EP6 FIFO, and commit it.
//
void fifo_send(void) {
EP6FIFOBUF[0] = 0x00;
EP6FIFOBUF[1] = 0x01;
EP6FIFOBUF[2] = 0x00;
EP6FIFOBUF[3] = 0x00;
EP6FIFOBUF[4] = 0x00;
EP6FIFOBUF[5] = sendCount++;
SYNCDELAY(); EP6BCH = 0;
SYNCDELAY(); EP6BCL = 6;
}
// Called repeatedly while the device is idle
//
void main_loop(void) {
if ( !(EP2468STAT & bmEP6EMPTY) ) {
fifo_send();
}
if ( some_other_condition() ) {
fifo_send();
}
}
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