https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63175
--- Comment #23 from rguenther at suse dot de <rguenther at suse dot de> --- On March 2, 2015 7:13:25 PM CET, "msebor at gcc dot gnu.org" <gcc-bugzi...@gcc.gnu.org> wrote: >https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63175 > >--- Comment #22 from Martin Sebor <msebor at gcc dot gnu.org> --- >(In reply to rguent...@suse.de from comment #21) >> >g: >> > .quad .L.g,.TOC.@tocbase >> > .previous >> > .type g, @function >> >.L.g: >> > addis 9,2,.LC1@toc@ha >> > addis 10,2,.LC0@toc@ha >> > addi 9,9,.LC1@toc@l >> > lxvw4x 32,0,9 >> > ld 9,.LC0@toc@l(10) >> > li 10,4 >> > stxvw4x 32,9,10 >> >> But isn't this simply wrong-code?! > >I don't see anything wrong with it. The load seems straightforward >enough and, >AFAICS, the store code matches the stxvw4x example in the PowerISA 2.07 >reference (in Storing an Unaligned Quadword to Big-Endian Storage on >page 360). > r9 is the address of B and r10 is the byte offset of B[1] from B. Ah, i only tested with altivec as noted in the bug description. I'll check with vsx tomorrow.
