[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

--- Comment #5 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Initial analysis is that ext-dce is fine at least as far as the RTL is
concerned.   Will need to look at combine next.