https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80770
--- Comment #6 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So RISC-V will generate good code for this with a relatively small target
dependent change that takes us in a direction we want to be going anyway.
To fix more generally I think this turns into a simplify-rtx problem:
Failed to match this instruction:
(parallel [
(set (reg:QI 110)
(ior:QI (and:QI (reg:QI 104 [ *s_4(D) ])
(const_int -2 [0xfffffffffffffffe]))
(and:QI (not:QI (reg:QI 104 [ *s_4(D) ]))
(const_int 1 [0x1]))))
(clobber (reg:CC 17 flags))
])
ISTM that's just a bit flip on the LSB of (reg 104). So simplify-rtx is the
first place I'd be looking to fix this.
