https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80770
--- Comment #8 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Further progress for RISC-V will be dependent upon simplifying something like
this:
(set (reg:DI 153)
(ior:DI (and:DI (reg:DI 140 [ *s_4(D) ])
(const_int 254 [0xfe]))
(and:DI (not:DI (reg:DI 140 [ *s_4(D) ]))
(const_int 1 [0x1]))))
It's crucial to realize that the first argument to the two AND expressions is
the same pseudo and that the constants are of the right form -- the first turns
off all the bits that are on in the latter.
Under those conditions it should simpify into something like:
(set (reg:SI 153)
(and:SI
(xor:SI (reg:SI 140 [ *s_4(D) ]) (const_int 1 [0x1]))
(const_int 255 [0xff])))
Which ultimately allows us to do a 4->2 split.
