[Bug rtl-optimization/122735] [16 regression] RISCV: ICE during RTL pass: combine

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122735

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://gcc.gnu.org/bugzill
                   |                            |a/show_bug.cgi?id=93738

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Definitely exposed by r16-5022-ga50b4406e5d64adb .

But the non-simplified const REG_EQUAL has been there since 8


(insn 9 7 10 2 (set (reg:SI 82)
        (lshiftrt:SI (reg:SI 80 [ d ])
            (const_int 32 [0x20]))) "/app/example.cpp":5 148 {lshrsi3}
     (expr_list:REG_EQUAL (lshiftrt:SI (const_int 19 [0x13])
            (const_int 32 [0x20]))
        (expr_list:REG_DEAD (reg:SI 81)
            (expr_list:REG_DEAD (reg:SI 80 [ d ])
                (nil)))))