[Bug target/122769] RISC-V: Short branch can be elided for alu op

[vineetg at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122769

--- Comment #12 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
So for now, the test in question is in
gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c

-O2 -march=rv64gc_zbb_zicond

long
test_ShiftLeft_eqz (long x, long y, long z, long c)
{
  if (c)
    x = y << z;
  else
    x = y;
  return x;
}

It is failing in ifcvt: noce_bbs_ok_for_cond_zero_arith () because it only
handles REG () for "a" and "b", while we have a subreg.

(gdb) call debug_rtx(cond)
(eq (reg/v:DI 139 [ c ])
    (const_int 0 [0]))

(gdb) call debug_rtx(a)
(ashift:DI (reg/v:DI 137 [ y ])
    (subreg:QI (reg/v:DI 138 [ z ]) 0))

(gdb) call debug_rtx(b)
(reg/v:DI 137 [ y ])

Looks like we need to extract subreg bits from Vrull patch afterall.