[Bug target/123521] [14/15/16 Regression] LoongArch64: ICE at -O1/O2/O3 during RTL pass: expand

[chenglulu at loongson dot cn via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123521

chenglulu <chenglulu at loongson dot cn> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |chenglulu at loongson dot cn

--- Comment #1 from chenglulu <chenglulu at loongson dot cn> ---
The following modifications can fix this problem:

```
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 836a210e02b..c4222d0d109 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10438,27 +10438,11 @@ loongarch_expand_vector_init_same (rtx target, rtx
vals, unsigned nvar)

   if (imode == GET_MODE (same))
     temp = same;
-  else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD)
-    {
-      if (GET_CODE (same) == MEM)
-       {
-         rtx reg_tmp = gen_reg_rtx (GET_MODE (same));
-         loongarch_emit_move (reg_tmp, same);
-         temp = simplify_gen_subreg (imode, reg_tmp, GET_MODE (reg_tmp), 0);
-       }
-      else
-       temp = simplify_gen_subreg (imode, same, GET_MODE (same), 0);
-    }
   else
     {
-      if (GET_CODE (same) == MEM)
-       {
-         rtx reg_tmp = gen_reg_rtx (GET_MODE (same));
-         loongarch_emit_move (reg_tmp, same);
-         temp = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp));
-       }
-      else
-       temp = lowpart_subreg (imode, same, GET_MODE (same));
+           rtx reg_tmp = gen_reg_rtx (imode);
+           loongarch_emit_move (reg_tmp, same);
+           temp = simplify_gen_subreg (imode, reg_tmp, GET_MODE (reg_tmp), 0);
     }


```