[Bug target/123521] [14/15/16 Regression] LoongArch64: ICE at -O1/O2/O3 during RTL pass: expand

[chenglulu at loongson dot cn via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123521

--- Comment #2 from chenglulu <chenglulu at loongson dot cn> ---
```
typedef long long v4i64 __attribute__ ((vector_size (32), aligned (32)));
extern long long *x_si;
v4i64
test (void)
{
  v4i64 a = { x_si[1], x_si[0], 0x411, 0x411 };
  return a;
}
```

This small test case can reproduce the problem.

# ./gcc/cc1 test.c -o test.s -O1 -msimd=lasx