https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115042
Vladimir Makarov <vmakarov at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |vmakarov at gcc dot gnu.org
--- Comment #6 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Richard Earnshaw from comment #5)
>
> Arm has 15 GP registers, but one of those is SP and a second is needed for
> the frame pointer at -O0, so there are at most 13 GP regs available. It
> wouldn't surprise me if the compiler needs at least 3 regs for its own
> needs, so I'd be inclined to think that this code is at best flaky.
I see there are enough registers to satisfy the constraints.
The problem is that the arm sub-target has 2 insn stores involving low and high
regs and LRA chooses lo regs as the store with low regs has less cost and the
asm clobbers contain low hard regs.
LRA chooses insn alternatives independently from reg class pressures. I
suspect reload pass does the same and probably has the same problem.
I think it would be hard to fix it but I'll work on it because probably some
other targets can have the same problem.
