https://gcc.gnu.org/g:44536104696e5d665a5b598144582acb8a110002
commit r16-3168-g44536104696e5d665a5b598144582acb8a110002
Author: Pan Li <pan2...@intel.com>
Date: Mon Aug 4 09:54:34 2025 +0800
RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR
cost 0, 1 and 15
Add asm dump check and run test for vec_duplicate + vmerge.vvm
combine to vmerge.vxm, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c | 10 ++
.../riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c | 10 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 22 +++
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c | 15 ++
.../riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c | 15 ++
.../riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c | 15 ++
.../riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c | 15 ++
18 files changed, 398 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c
new file mode 100644
index 000000000000..3770c96fdafd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+#define T int16_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c
new file mode 100644
index 000000000000..1016100d1257
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+#define T int32_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c
new file mode 100644
index 000000000000..6df25b6de4c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+#define T int64_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c
new file mode 100644
index 000000000000..738adb75be14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+#define T int8_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c
new file mode 100644
index 000000000000..340a4aac6fcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+#define T int16_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c
new file mode 100644
index 000000000000..cba682257f8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+#define T int32_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c
new file mode 100644
index 000000000000..45efd3a41021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+#define T int64_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c
new file mode 100644
index 000000000000..b6f00005f2f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+#define T int8_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c
new file mode 100644
index 000000000000..c1e1b3042ba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+#define T int16_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c
new file mode 100644
index 000000000000..a626720e753d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+#define T int32_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c
new file mode 100644
index 000000000000..17dc5bf8a275
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+#define T int64_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c
new file mode 100644
index 000000000000..2aee2cf3ef00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+#define T int8_t
+
+DEF_VX_MERGE_0_WRAP(T)
+
+/* { dg-final { scan-assembler-not {vmerge.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index 4a9daff31386..353ee167c376 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -429,4 +429,26 @@ DEF_AVG_CEIL(int32_t, int64_t)
DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \
DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \
+/* For some special cases cannot be normalized as above */
+
+#define DEF_VX_MERGE_0(T) \
+void \
+test_vx_merge_##T##_case_0 (T * restrict out, T * restrict in, \
+ T x, unsigned n) \
+{ \
+ for (unsigned i = 0; i < n; i++) \
+ { \
+ if (i % 2 == 0) \
+ out[i] = x; \
+ else \
+ out[i] = in[i]; \
+ } \
+}
+
+#define DEF_VX_MERGE_0_WRAP(T) DEF_VX_MERGE_0(T)
+
+#define RUN_VX_MERGE_0(T, out, in, x, n) \
+ test_vx_merge_##T##_case_0(out, in, x, n)
+#define RUN_VX_MERGE_0_WRAP(T, out, in, x, n) RUN_VX_MERGE_0(T, out, in, x, n)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 626347cb386a..e385bf21ec7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -5690,4 +5690,200 @@ int64_t TEST_BINARY_DATA(int64_t, avg_ceil)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, merge)[][3][N] =
+{
+ {
+ { 0 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 4, 4, 4, 4,
+ },
+ {
+ 0, 2, 0, 2,
+ 0, 1, 0, 1,
+ 0, 0, 0, 0,
+ 0, 4, 0, 4,
+ },
+ },
+ {
+ { 127 },
+ {
+ 127, 127, 127, 127,
+ -128, -128, -128, -128,
+ -127, -127, -127, -127,
+ 1, 1, 1, 1,
+ },
+ {
+ 127, 127, 127, 127,
+ 127, -128, 127, -128,
+ 127, -127, 127, -127,
+ 127, 1, 127, 1,
+ },
+ },
+ {
+ {-128 },
+ {
+ 0, 0, 0, 0,
+ -128, -128, -128, -128,
+ 126, 126, 126, 126,
+ 127, 127, 127, 127,
+ },
+ {
+ -128, 0, -128, 0,
+ -128, -128, -128, -128,
+ -128, 126, -128, 126,
+ -128, 127, -128, 127,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, merge)[][3][N] =
+{
+ {
+ { 0 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 4, 4, 4, 4,
+ },
+ {
+ 0, 2, 0, 2,
+ 0, 1, 0, 1,
+ 0, 0, 0, 0,
+ 0, 4, 0, 4,
+ },
+ },
+ {
+ { 32767 },
+ {
+ 32767, 32767, 32767, 32767,
+ -32768, -32768, -32768, -32768,
+ -32767, -32767, -32767, -32767,
+ 1, 1, 1, 1,
+ },
+ {
+ 32767, 32767, 32767, 32767,
+ 32767, -32768, 32767, -32768,
+ 32767, -32767, 32767, -32767,
+ 32767, 1, 32767, 1,
+ },
+ },
+ {
+ {-32768 },
+ {
+ 0, 0, 0, 0,
+ -32768, -32768, -32768, -32768,
+ 32766, 32766, 32766, 32766,
+ 32767, 32767, 32767, 32767,
+ },
+ {
+ -32768, 0, -32768, 0,
+ -32768, -32768, -32768, -32768,
+ -32768, 32766, -32768, 32766,
+ -32768, 32767, -32768, 32767,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, merge)[][3][N] =
+{
+ {
+ { 0 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 4, 4, 4, 4,
+ },
+ {
+ 0, 2, 0, 2,
+ 0, 1, 0, 1,
+ 0, 0, 0, 0,
+ 0, 4, 0, 4,
+ },
+ },
+ {
+ { 2147483647 },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ -2147483647, -2147483647, -2147483647, -2147483647,
+ 1, 1, 1, 1,
+ },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483647, -2147483648, 2147483647, -2147483648,
+ 2147483647, -2147483647, 2147483647, -2147483647,
+ 2147483647, 1, 2147483647, 1,
+ },
+ },
+ {
+ {-2147483648 },
+ {
+ 0, 0, 0, 0,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ 2147483646, 2147483646, 2147483646, 2147483646,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ },
+ {
+ -2147483648, 0, -2147483648, 0,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ -2147483648, 2147483646, -2147483648, 2147483646,
+ -2147483648, 2147483647, -2147483648, 2147483647,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, merge)[][3][N] =
+{
+ {
+ { 0 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 4, 4, 4, 4,
+ },
+ {
+ 0, 2, 0, 2,
+ 0, 1, 0, 1,
+ 0, 0, 0, 0,
+ 0, 4, 0, 4,
+ },
+ },
+ {
+ { 9223372036854775807ull },
+ {
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ -9223372036854775807ull, -9223372036854775807ull,
-9223372036854775807ull, -9223372036854775807ull,
+ 1, 1,
1, 1,
+ },
+ {
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ 9223372036854775807ull, -9223372036854775808ull,
9223372036854775807ull, -9223372036854775808ull,
+ 9223372036854775807ull, -9223372036854775807ull,
9223372036854775807ull, -9223372036854775807ull,
+ 9223372036854775807ull, 1,
9223372036854775807ull, 1,
+ },
+ },
+ {
+ {-9223372036854775808ull },
+ {
+ 0, 0,
0, 0,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ 9223372036854775806ull, 9223372036854775806ull,
9223372036854775806ull, 9223372036854775806ull,
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ },
+ {
+ -9223372036854775808ull, 0,
-9223372036854775808ull, 0,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ -9223372036854775808ull, 9223372036854775806ull,
-9223372036854775808ull, 9223372036854775806ull,
+ -9223372036854775808ull, 9223372036854775807ull,
-9223372036854775808ull, 9223372036854775807ull,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c
new file mode 100644
index 000000000000..28458744f52d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+#define NAME merge
+
+DEF_VX_MERGE_0_WRAP(T)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c
new file mode 100644
index 000000000000..57545fb0d9a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME merge
+
+DEF_VX_MERGE_0_WRAP(T)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c
new file mode 100644
index 000000000000..fbcb0868ddef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+#define NAME merge
+
+DEF_VX_MERGE_0_WRAP(T)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c
new file mode 100644
index 000000000000..0c5500a34588
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+#define NAME merge
+
+DEF_VX_MERGE_0_WRAP(T)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n)
+
+#include "vx_binary_run.h"
