https://gcc.gnu.org/g:430ec2bbede26188eb56d09a9e37168f8741059a
commit 430ec2bbede26188eb56d09a9e37168f8741059a Author: Michael Meissner <[email protected]> Date: Tue Sep 9 22:28:11 2025 -0400 Revert changes Diff: --- gcc/config/rs6000/rs6000.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 82214945ccdf..a81758e62a02 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8226,28 +8226,28 @@ (define_insn "*movhf_internal" [(set (match_operand:HF 0 "nonimmediate_operand" - "=wa, wa, Z, r, r, + "=wa, wa, Z, r, r, m, r, wa, wa, r") (match_operand:HF 1 "any_operand" - "wa, Z, wa, r, m, - r, wa, r, j, j"))] + "wa, Z, wa, r, m, + r, wa, r, j, j"))] "TARGET_IEEE16 && (gpc_reg_operand (operands[0], HFmode) || gpc_reg_operand (operands[1], HFmode))" "@ xxlor %x0,%x1,%x1 - lxsihzx %x0,%y1 - stxsihx %x1,%y0 + lxsiwzx %x0,%y1 + stxsiwx %x1,%y0 mr %0,%1 - lhz%U1%X1 %0,%1 - sth%U0%X0 %1,%0 + lwz%U1%X1 %0,%1 + stw%U0%X0 %1,%0 mfvsrwz %0,%x1 mtvsrwz %x0,%1 xxspltib %x0,0 li %0,0" - [(set_attr "type" "vecsimple, fpload, fpstore, *, load, - store, mtvsr, mfvsr, vecsimple, *")]) + [(set_attr "type" "vecsimple, fpload, fpstore, *, load, + store, mtvsr, mfvsr, vecsimple, *")])
