https://gcc.gnu.org/g:b5c86404a15d744620d83d6f37c77851dd00c41b
commit b5c86404a15d744620d83d6f37c77851dd00c41b Author: Michael Meissner <[email protected]> Date: Wed Oct 1 00:47:52 2025 -0400 Change -mieee16 to -mfloat16; Allow use on power8. 2025-10-01 Michael Meissner <[email protected]> gcc/ * config/rs6000/altivec.md (altivec_vsplth_v8bf): Use xxspltw instead of vspltw. Diff: --- gcc/config/rs6000/altivec.md | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index ba47c4d597ab..f50da15b08dc 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2480,13 +2480,22 @@ ;; Splat instruction needed to allow conversion of __bfloat16 ;; (i.e. BFmode) to SFmode/DFmode. +;; (define_insn "altivec_vsplth_v8bf" +;; [(set (match_operand:V8BF 0 "register_operand" "=v") +;; (unspec:V8BF [(match_operand:BF 1 "register_operand" "v") +;; (match_operand:QI 2 "const_0_to_7_operand" "i")] +;; UNSPEC_VSPLT_DIRECT))] +;; "TARGET_BFLOAT16" +;; "vsplth %0,%1,%2" +;; [(set_attr "type" "vecperm")]) + (define_insn "altivec_vsplth_v8bf" - [(set (match_operand:V8BF 0 "register_operand" "=v") - (unspec:V8BF [(match_operand:BF 1 "register_operand" "v") + [(set (match_operand:V8BF 0 "register_operand" "=wa") + (unspec:V8BF [(match_operand:BF 1 "register_operand" "wa") (match_operand:QI 2 "const_0_to_7_operand" "i")] UNSPEC_VSPLT_DIRECT))] "TARGET_BFLOAT16" - "vsplth %0,%1,%2" + "xxspltw %x0,%x1,1" [(set_attr "type" "vecperm")]) (define_insn "altivec_vspltis<VI_char>"
