The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to: 57a4a63e448c... RISC-V: Fix indexed store output template [PR123780].
It previously pointed to: 65c3143f176a... RISC-V: Fix indexed store output template [PR123780]. Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- 65c3143... RISC-V: Fix indexed store output template [PR123780]. 43f1ba8... RISC-V: Add zvfbfmin to tt-ascalon-d8's extension list [PR1 6b9a6fa... forwprop: More nop-conversion handling [PR123731]. f7c034a... RISC-V: Correct builtin registration order [PR123279]. 6844a7d... [PR rtl-optimization/123380] Avoid creating bogus SUBREG in aac9166... [RISC-V][PR target/123626] Fix VXRM state after calls b0e204b... [RISC-V][PR rtl-optimization/121787] Work around bad cfglay efb1f1d... [PR target/113666] Simplify VEC_EXTRACT from a uniform vect 5f40721... doc, riscv: Clean up documentation of RISC-V options [PR122 92e7dd6... vect: Make SELECT_VL a convert optab. 81a3128... forwprop: Allow nop conversions for vector constructor. f5478a8... forwprop: allow subvectors in simplify_vector_constructor ( a3da3e3... forwprop: Check type conversion in pack/unpack [PR123117]. e4b033e... [PR target/121778] Improving rotation detection 86ed53e... [PR123092, LRA]: Reprocess insn after equivalence substitut c98183b... Fix RISC-V test after recent vectorizer changes a2eefa8... RISC-V: Enable the ZD constraint only when xmipscbop is ena f6f71ac... match: Add simplification of `(a*zero_one_valued_p) & b` if 672342e... ifcvt: Improve `cmp?a&b:a` to try with -1 [PR123312] 382dbf9... forwprop: Fix type mismatch in vec constructor [PR123525]. c1d9bcc... if-conv: Prevent vector types in scalar cond reduction [PR1 9499bfc... rtlanal: Determine nonzero bits of popcount from operand [P e22662d... VN: Fix VN ICE for large _BitInt types 6cf6553... RISC-V: Add support for _BitInt [PR117581] 89e24f2... forwprop: Use ssizetype for mask [PR123414]. a80d633... RISC-V: Update tt-ascalon-d8's extension list [PR123492] 1a4a0c0... ifcvt: Reject inner floating modes of a subreg for noce_try 3d83689... [RISC-V] Clamp long reservations to 7c 3c73ba8... RISC-V: -mrvv-max-lmul=conv-dynamic [PR122846]. 3d381dc... [PATCH v3] match.pd: popcount(X & -X) -> -X != 0 [PR102486] 73b3b88... [RISC-V] Restore inline expansion of block moves on RISC-V 5f55eda... [PATCH v1 2/2] RISC-V: Add run test case for vwadd/vwsub wx b326613... [PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for an e4f5c93... RISC-V: Adjust the asm check of vx_vf due to middle-end cha ff5b659... Vect: Adjust depth_limit of vec_slp_has_scalar_use from 2 t 46d3e66... Partially revert patch that made VXRM a global register on 54caf03... [PR target/123010] Simplify shift of sign extracted field t 1359e21... [RISC-V][PR target/121485] Fix mode on Zvkned lmul extendin 8340bd2... [RISC-V][PR target/123318] Use a Pmode temporary for output d4d592b... ifcvt: Allow non-comparisons against 0 in noce_try_cond_zer 19beb34... ifcvt: Handle lowpart subregs if noce_emit_cmove fails in n 64e358c... ifcvt: cleanup if_info->cond usage in noce_try_cond_zero_ar 6b4af6e... simplify-rtx: Fix up (ne (ior (ne x 0) y) 0) simplification 1b7ccd8... Revert "ifcvt: Move noce_try_cond_zero_arith last" 3c68ef6... [RISC-V][PR target/123283] Wrap naked REG operands with a U 39b1c32... doc: make regenerate-opt-urls 84c5701... doc, riscv: Clean up RISC-V extensions documentation a78127a... RISC-V: Add test for vec_duplicate + vmsleu.vv combine with ca0a993... RISC-V: Combine vec_duplicate + vmsleu.vv to vmsleu.vx on G 45f64a7... ifcvt: Move noce_try_cond_zero_arith last 459de01... ifcvt: Only allow scalar integral modes for noce_try_cond_z 5b865a0... [committed][RISC-V][PR target/123274] Add missing condition 704eabc... [RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 s d289dbd... [RISC-V][PATCH] Adjust clmul latency in Spacemit X60 schedu 8b1fb46... ifcvt: Fix noce_try_cond_zero_arith after get_base_reg chan 3e1d0f3... [RISC-V][V2] Improve spill code for RVV slightly to fix reg 11e3841... ifcvt: cond zero arith: handle subreg for shift count aa6d5e4... ifcvt: cond zero arith: elide short forward branch for sign cb4770a... ifcvt: cond zero arith: re-expand output pattern [NFC] 896d600... ifcvt: cond zero arith: factor out common noce_emit_czero e 9af3427... ifcvt: cond zero arith: opencode helper noce_bbs_ok_for_con 7bb2f16... [RISC-V][V2] Improve spill code for RVV slightly to fix reg ce66f28... RISC-V: Fix overflow check in interleave pattern [PR122970] ff2f1e2... RISC-V: Testsuite fixes. 572d283... RISC-V: Generic vec_extract via subreg. d839e61... RISC-V: Add VLS modes to autovec iterators. 2f31ce3... RISC-V: Rename vector-mode related functions. 189894e... RISC-V: Change gather/scatter iterators. 12c0351... Fix various RISC-V testsuite regressions after volatile pat 96311fb... [PATCH] RISC-V: Rename UPPERCAE_NAME to UPPERCASE_NAME 9f56200... RISC-V: Add test for vec_duplicate + vmslt.vv combine with 0d62cd0... RISC-V: Combine vec_duplicate + vmslt.vv to vmslt.vx on GR2 347c220... RISC-V: Regenerate opt urls. 7fceee3... RISC-V: -mmax-vectorization. 7a83aa8... vect: Add vect-scalar-cost-multiplier for SLP. dbd2fd4... middle-end: Add new parameter to scale scalar loop costing 162cebc... RISC-V: Pragma target [PR115325]. 3cd9962... RISC-V: Implement mask reduction. 087111b... [riscv] avoid auipc overflow with large offsets [PR91420] cef7898... RISC-V: Add test for vec_duplicate + vmsltu.vv combine with 97e663c... RISC-V: Combine vec_duplicate + vmsltu.vv to vmsltu.vx on G d102971... RISC-V: Remove unused placeholder_p parameter from add_func 1eeff6a... [PATCH][PR target/122942] RISC-V: Add zifencei extension to 1634f44... riscv: RISCV backend, meet C++20 80db728... RISC-V: Emit \n\t at the end of instruction instead of ; fd2281e... RISC-V: Support --with-cpu d71ce5e... RISC-V: Add SpacemiT extension xsmtvdot c73d5fb... RISC-V: Run gen-riscv-ext-opt to regenerate riscv-ext.opt [ 3ab7897... RISC-V: Add Andes 45 series pipeline description. 5212b52... RISC-V: Add Andes 23 series pipeline description. a5a5f1e... RISC-V: Fix one typo result in pr121959-run-1 run failure a422357... Revert "[PATCH v3] RISC-V: Implement RISC-V profile macro s dcfc162... RISC-V: Add testcase for unsigned scalar SAT_MUL form 7 0041709... RISC-V: Add BF VLS modes and document iterators. 7db3b88... [PR rtl-optimization/122782] Fix out of range shift causing 1c5e178... [PR 122701] Emit fresh reg->reg copy rather than modifying 841f1ce... [PR118358, LRA]: Decrease pressure after issuing input relo f085534... RISC-V: Add RTL pass to combine cm.popret with zero return e968a25... [RISC-V] Fix trivial bootstrap failure on RISC-V f49b295... RISC-V: Add flag to adjust mem inlining threshold ee3ca44... [RISC-V] Add cpu and tuning structures for spacemit-x60 des 0e31a81... RISC-V: Remove gather scale and offset handling. e2959d8... [PR rtl-optimization/122575] Fix mode on optimized IOR comp 5f33452... RISC-V: Add test for vec_duplicate + vmsne.vv combine case 7207ce8... RISC-V: Add test for vec_duplicate + vmsne.vv combine case f5c4bef... [RISC-V] Avoid most calls to gen_extend_insn 199f9f9... [RISC-V] Drop scan-tests of marginal value 23fc235... RISC-V: Add missing member for andes_25_tune_info 4a270bc... Handle shift-pairs in ext-dce for targets without zero/sign 840a4f2... RISC-V: Add Andes 25 series pipeline description. f231af9... [RISC-V] Improve detection of packw 013077e... [RISC-V] Simplify riscv_extend_to_xmode_reg 6b0cf05... RISC-V: Add test for vec_duplicate + vmseq.vv combine case 5561f0e... RISC-V: Add test for vec_duplicate + vmseq.vv combine case 1bc9935... [RISC-V] Add testcase for shifted truthvalue 2f17976... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB 383dfe0... RISC-V: Add test for vec_duplicate + vwmaccu.vv combine wit 4bd731c... RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmac ae25859... [RISC-V] Ignore useless zero-initialization in conditional d95707e... [RISC-V][PR 121136] Improve various tests which only need t 5107294... RISC-V: testsuite: Fix pr119115.c. 563c0e2... [PR rtl-optimization/122536] Fix guard against variable bit 3ca5bd0... RISC-V: Fix the ABI of empty unions and zero length array i 6bdfb85... [RISC-V][PR tree-optimization/52345] Optimize testing multi 9e2dcc1... [RISC-V] Expose sign extension for 32 bit rotates by consta f5f8707... gcc: Drop junk vim backup file 05e88f5... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR 6c45153... [RISC-V] Reorder ready queue slightly to avoid unnecessary Summary of changes (added commits): ----------------------------------- 57a4a63... RISC-V: Fix indexed store output template [PR123780]. a007172... RISC-V: Add zvfbfmin to tt-ascalon-d8's extension list [PR1 2a5e3d1... forwprop: More nop-conversion handling [PR123731]. 54aa936... RISC-V: Correct builtin registration order [PR123279]. 45007c4... [PR rtl-optimization/123380] Avoid creating bogus SUBREG in 75319cb... [RISC-V][PR target/123626] Fix VXRM state after calls f50a7c1... [RISC-V][PR rtl-optimization/121787] Work around bad cfglay 4a3f873... [PR target/113666] Simplify VEC_EXTRACT from a uniform vect 407246a... doc, riscv: Clean up documentation of RISC-V options [PR122 f15b6b6... vect: Make SELECT_VL a convert optab. abea7aa... forwprop: Allow nop conversions for vector constructor. aa2ba2e... forwprop: allow subvectors in simplify_vector_constructor ( 631b6e1... forwprop: Check type conversion in pack/unpack [PR123117]. eccfa3e... [PR target/121778] Improving rotation detection 33cd3c0... [PR123092, LRA]: Reprocess insn after equivalence substitut 6691ab9... Fix RISC-V test after recent vectorizer changes 150b237... RISC-V: Enable the ZD constraint only when xmipscbop is ena f8304a0... match: Add simplification of `(a*zero_one_valued_p) & b` if 9730e5b... ifcvt: Improve `cmp?a&b:a` to try with -1 [PR123312] 3b65b8e... forwprop: Fix type mismatch in vec constructor [PR123525]. b6964ea... if-conv: Prevent vector types in scalar cond reduction [PR1 7946cbe... rtlanal: Determine nonzero bits of popcount from operand [P 26434d8... VN: Fix VN ICE for large _BitInt types 745eafd... RISC-V: Add support for _BitInt [PR117581] 9ff3f5b... forwprop: Use ssizetype for mask [PR123414]. 36311c4... RISC-V: Update tt-ascalon-d8's extension list [PR123492] 1d5ae46... ifcvt: Reject inner floating modes of a subreg for noce_try 6cfe2b0... [RISC-V] Clamp long reservations to 7c 8ddb9e7... RISC-V: -mrvv-max-lmul=conv-dynamic [PR122846]. 6171760... [PATCH v3] match.pd: popcount(X & -X) -> -X != 0 [PR102486] 12bd187... [RISC-V] Restore inline expansion of block moves on RISC-V 947f37c... [PATCH v1 2/2] RISC-V: Add run test case for vwadd/vwsub wx 0aa58bc... [PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for an 30571a1... RISC-V: Adjust the asm check of vx_vf due to middle-end cha 1aff976... Vect: Adjust depth_limit of vec_slp_has_scalar_use from 2 t 5ff9546... Partially revert patch that made VXRM a global register on 265cf28... [PR target/123010] Simplify shift of sign extracted field t 15b24bc... [RISC-V][PR target/121485] Fix mode on Zvkned lmul extendin 39ebc29... [RISC-V][PR target/123318] Use a Pmode temporary for output 8f9212c... ifcvt: Allow non-comparisons against 0 in noce_try_cond_zer 1937864... ifcvt: Handle lowpart subregs if noce_emit_cmove fails in n 3cda579... ifcvt: cleanup if_info->cond usage in noce_try_cond_zero_ar fd796cf... simplify-rtx: Fix up (ne (ior (ne x 0) y) 0) simplification ee0b053... Revert "ifcvt: Move noce_try_cond_zero_arith last" 7fc51d6... [RISC-V][PR target/123283] Wrap naked REG operands with a U 02fd5c5... doc: make regenerate-opt-urls 1985fed... doc, riscv: Clean up RISC-V extensions documentation 3d83984... RISC-V: Add test for vec_duplicate + vmsleu.vv combine with 87cf1ed... RISC-V: Combine vec_duplicate + vmsleu.vv to vmsleu.vx on G 1c46218... ifcvt: Move noce_try_cond_zero_arith last 7b4ec20... ifcvt: Only allow scalar integral modes for noce_try_cond_z 406fc13... [committed][RISC-V][PR target/123274] Add missing condition bf264db... [RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 s 76ee564... [RISC-V][PATCH] Adjust clmul latency in Spacemit X60 schedu 809650b... ifcvt: Fix noce_try_cond_zero_arith after get_base_reg chan 3a7f962... [RISC-V][V2] Improve spill code for RVV slightly to fix reg 9cd8c43... ifcvt: cond zero arith: handle subreg for shift count 8699592... ifcvt: cond zero arith: elide short forward branch for sign 878a13d... ifcvt: cond zero arith: re-expand output pattern [NFC] a579f80... ifcvt: cond zero arith: factor out common noce_emit_czero e 4329b1e... ifcvt: cond zero arith: opencode helper noce_bbs_ok_for_con abdeaf3... [RISC-V][V2] Improve spill code for RVV slightly to fix reg 635393b... RISC-V: Fix overflow check in interleave pattern [PR122970] acbf8d2... RISC-V: Testsuite fixes. 0f67354... RISC-V: Generic vec_extract via subreg. 310c0eb... RISC-V: Add VLS modes to autovec iterators. 0626cd5... RISC-V: Rename vector-mode related functions. 1513dcb... RISC-V: Change gather/scatter iterators. 321ac9d... Fix various RISC-V testsuite regressions after volatile pat 46d9aba... [PATCH] RISC-V: Rename UPPERCAE_NAME to UPPERCASE_NAME 77369ad... RISC-V: Add test for vec_duplicate + vmslt.vv combine with f618d17... RISC-V: Combine vec_duplicate + vmslt.vv to vmslt.vx on GR2 c9c6862... RISC-V: Regenerate opt urls. 890428b... RISC-V: -mmax-vectorization. c1b028d... vect: Add vect-scalar-cost-multiplier for SLP. 14e3894... middle-end: Add new parameter to scale scalar loop costing 52d42df... RISC-V: Pragma target [PR115325]. 8f6ca0d... RISC-V: Implement mask reduction. 7fc8878... [riscv] avoid auipc overflow with large offsets [PR91420] e8e0b76... RISC-V: Add test for vec_duplicate + vmsltu.vv combine with f7b73b8... RISC-V: Combine vec_duplicate + vmsltu.vv to vmsltu.vx on G 8e5098b... RISC-V: Remove unused placeholder_p parameter from add_func 4726ae3... [PATCH][PR target/122942] RISC-V: Add zifencei extension to b51d8ba... riscv: RISCV backend, meet C++20 06e9cf4... RISC-V: Emit \n\t at the end of instruction instead of ; 8b3d6bc... RISC-V: Support --with-cpu f7b4e1d... RISC-V: Add SpacemiT extension xsmtvdot 6702a6b... RISC-V: Run gen-riscv-ext-opt to regenerate riscv-ext.opt [ d32721f... RISC-V: Add Andes 45 series pipeline description. e372b13... RISC-V: Add Andes 23 series pipeline description. 03046c0... RISC-V: Fix one typo result in pr121959-run-1 run failure 67104a8... Revert "[PATCH v3] RISC-V: Implement RISC-V profile macro s 792b2ef... RISC-V: Add testcase for unsigned scalar SAT_MUL form 7 97487b5... RISC-V: Add BF VLS modes and document iterators. 43eefa1... [PR rtl-optimization/122782] Fix out of range shift causing b67f26c... [PR 122701] Emit fresh reg->reg copy rather than modifying b61a5af... [PR118358, LRA]: Decrease pressure after issuing input relo 760abec... RISC-V: Add RTL pass to combine cm.popret with zero return a3b46ff... [RISC-V] Fix trivial bootstrap failure on RISC-V 27fad66... RISC-V: Add flag to adjust mem inlining threshold aa4314f... [RISC-V] Add cpu and tuning structures for spacemit-x60 des 3f5368b... RISC-V: Remove gather scale and offset handling. 57673f2... [PR rtl-optimization/122575] Fix mode on optimized IOR comp 1671089... RISC-V: Add test for vec_duplicate + vmsne.vv combine case 6a009ef... RISC-V: Add test for vec_duplicate + vmsne.vv combine case 4db053d... [RISC-V] Avoid most calls to gen_extend_insn 4fc97ca... [RISC-V] Drop scan-tests of marginal value 56fb774... RISC-V: Add missing member for andes_25_tune_info 7da7204... Handle shift-pairs in ext-dce for targets without zero/sign a51a117... RISC-V: Add Andes 25 series pipeline description. 95d13d0... [RISC-V] Improve detection of packw f1248f8... [RISC-V] Simplify riscv_extend_to_xmode_reg edb1838... RISC-V: Add test for vec_duplicate + vmseq.vv combine case 33e1f1d... RISC-V: Add test for vec_duplicate + vmseq.vv combine case 73b4d4c... [RISC-V] Add testcase for shifted truthvalue 29d1486... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB 26f187f... RISC-V: Add test for vec_duplicate + vwmaccu.vv combine wit c13e9e7... RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmac 97d982e... [RISC-V] Ignore useless zero-initialization in conditional 460fbe5... [RISC-V][PR 121136] Improve various tests which only need t fb79fc5... RISC-V: testsuite: Fix pr119115.c. 6bd0acf... [PR rtl-optimization/122536] Fix guard against variable bit c5ec331... RISC-V: Fix the ABI of empty unions and zero length array i 858f8f0... [RISC-V][PR tree-optimization/52345] Optimize testing multi 82eca05... [RISC-V] Expose sign extension for 32 bit rotates by consta f71e858... gcc: Drop junk vim backup file 3903d79... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR 05df5aa... [RISC-V] Reorder ready queue slightly to avoid unnecessary bc6238f... tree-optimization/122502 - avoid folding during imm use wal
