https://gcc.gnu.org/g:07e4d4aee3f0c13588af4ef596f135625b4cb8a9
commit 07e4d4aee3f0c13588af4ef596f135625b4cb8a9 Author: Michael Meissner <[email protected]> Date: Thu Jun 25 04:13:22 2026 -0400 Optimize __bfloat16 scalar code. Optimize __bfloat16 binary operations. Unlike _Float16 where we have instructions to convert between HFmode and SFmode as scalar values, with BFmode, we only have vector conversions. Thus to do: __bfloat16 a, b, c; a = b + c; the GCC compiler generates the following code: lxsihzx 0,4,2 // load __bfloat16 value b lxsihzx 12,5,2 // load __bfloat16 value c xxsldwi 0,0,0,1 // shift b into bits 16..31 xxsldwi 12,12,12,1 // shift c into bits 16..31 xvcvbf16spn 0,0 // vector convert b into V4SFmode xvcvbf16spn 12,12 // vector convert c into V4SFmode xscvspdpn 0,0 // convert b into SFmode scalar xscvspdpn 12,12 // convert c into SFmode scalar fadds 0,0,12 // add b+c xscvdpspn 0,0 // convert b+c into SFmode memory format xvcvspbf16 0,0 // convert b+c into BFmode memory format stxsihx 0,3,2 // store b+c Using the following combiner patterns that are defined in this patch, the code generated would be: lxsihzx 12,4,2 // load __bfloat16 value b lxsihzx 0,5,2 // load __bfloat16 value c xxspltw 12,12,1 // shift b into bits 16..31 xxspltw 0,0,1 // shift c into bits 16..31 xvcvbf16spn 12,12 // vector convert b into V4SFmode xvcvbf16spn 0,0 // vector convert c into V4SFmode xvaddsp 0,0,12 // vector b+c in V4SFmode xvcvspbf16 0,0 // convert b+c into BFmode memory format stxsihx 0,3,2 // store b+c We cannot just define insns like 'addbf3' to keep the operation as BFmode because GCC will not generate these patterns unless the user uses -Ofast. Without -Ofast, it will always convert BFmode into SFmode. 2026-06-25 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.cc (bfloat16_operation_as_v4sf): New function to optimize __bfloat16 scalar operations. * config/rs6000/float16.md (xvcvbf16spn_bf): New insn. (bfloat16_binary_op_internal1): New __bfloat16 scalar combiner insns. (bfloat16_binary_op_internal2): Likewise. (bfloat16_fma_internal1): Likewise. (bfloat16_fma_internal2): Likewise. (bfloat16_fms_internal1): Likewise. (bfloat16_fms_internal2): Likewise. (bfloat16_nfma_internal1): Likewise. (bfloat16_nfma_internal2): Likewise. (bfloat16_nfms_internal3): Likewise. * config/rs6000/predicates.md (fp16_reg_or_constant_operand): New predicate. (bfloat16_v4sf_operand): Likewise. (bfloat16_bf_operand): Likewise. * config/rs6000/rs6000-protos.h (bfloat16_operation_as_v4sf): New declaration. Diff: --- gcc/config/rs6000/predicates.md | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index f549c762eb51..41e150fb2a80 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -2374,7 +2374,6 @@ return constant_generates_xxspltiw (&vsx_const); }) -<<<<<<< HEAD ;; Return 1 if this is a 16-bit floating point operand that can be used ;; in an add, subtract, or multiply operation that uses the vector @@ -2451,5 +2450,3 @@ return false; }) -======= ->>>>>>> 657f8abb6c6 (Add initial 16-bit floating point support.)
