https://gcc.gnu.org/g:ca5e88d7531aa673a937007a0e21a141eee743e9
commit r17-4544-gca5e88d7531aa673a937007a0e21a141eee743e9 Author: Pan Li <[email protected]> Date: Fri Sep 18 16:26:51 2026 +0800 RISC-V: Allow RVV register overlap for vfwadd.wv There are two constraint of vfwadd.wv, aka 2 * SEW = 2 * SEW + SEW form. 1. The vs1 can overlap to the highest part of the vd. 2. The vs1 cannot overlap the group of vs2. gcc/ChangeLog: * config/riscv/constraints.md (Wn4): New constraint for the vector register which doesn't overlap the register group of the operand 4. * config/riscv/vector.md: Take the Wn4 constraint for the operand 3 and the Wvr constraint for the operand 4 of the vfwadd.wv. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/constraints.md | 6 ++++++ gcc/config/riscv/vector.md | 20 ++++++++++---------- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 38f46d8fec5c..666d5a246ceb 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -254,6 +254,12 @@ "riscv_vector::riscv_v_widen_non_overlap_constraint_ok (regno, mode, ref_regno, ref_mode)" "3") +;; Same as Wn3 but target operand 4, aka ref_regno and ref_mode come from operand 4. +(define_register_constraint "Wn4" "TARGET_VECTOR ? V_REGS : NO_REGS" + "Vector reg not overlapping the operand 4 register group" + "riscv_vector::riscv_v_widen_non_overlap_constraint_ok (regno, mode, ref_regno, ref_mode)" + "4") + ;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov<mode>". ;; VLENB is a run-time constant which represent the vector register length in bytes. ;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register length in bytes. diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 83a2c8f346d7..023668ceadae 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7345,23 +7345,23 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_single_widen_add<mode>" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VWEXTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rvl, rvl") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (match_operand 9 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1,Wc1, vm, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTF (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")) - (match_operand:VWEXTF 3 "register_operand" " vr, vr")) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr,Wvr,Wvr")) + (match_operand:VWEXTF 3 "register_operand" "Wn4,Wn4,Wn4,Wn4")) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwadd.wv\t%0,%3,%4%p1" [(set_attr "type" "vfwalu")
