https://gcc.gnu.org/g:be4d7029a2b4398305fdc82d134f2dd04138ee10
commit be4d7029a2b4398305fdc82d134f2dd04138ee10 Author: Tobias Burnus <[email protected]> Date: Mon Oct 19 08:10:00 2026 +0200 ChangeLog.omp bump Diff: --- contrib/ChangeLog.omp | 5 + gcc/ChangeLog.omp | 230 +++++++++++++++++++++++++++++++++++++++++++- gcc/DATESTAMP.omp | 2 +- gcc/cp/ChangeLog.omp | 16 +++ gcc/testsuite/ChangeLog.omp | 10 ++ libgomp/ChangeLog.omp | 21 ++++ 6 files changed, 282 insertions(+), 2 deletions(-) diff --git a/contrib/ChangeLog.omp b/contrib/ChangeLog.omp index 109b87f62af9..7a26eccefad5 100644 --- a/contrib/ChangeLog.omp +++ b/contrib/ChangeLog.omp @@ -1,3 +1,8 @@ +2026-10-19 Tobias Burnus <[email protected]> + + * gcc-changelog/git_update_version.py: Add + 242479bea82be90e0acfc3 to ignored_commits + 2026-07-09 Tobias Burnus <[email protected]> * gcc-changelog/git_repository.py (parse_git_revisions): Optional diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp index 72ab4eeb87bf..1d449714f729 100644 --- a/gcc/ChangeLog.omp +++ b/gcc/ChangeLog.omp @@ -1,3 +1,231 @@ +2026-10-15 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-10-15 Andrew Stubbs <[email protected]> + + * config/gcn/gcn.md (UNSPEC_PAIR): New. + (X): Add vector modes. + (ATOMICMODE): New mode iterator. + (atomic_fetch_<bare_mnemonic><mode>): Use ATOMICMODE iterator. Add Rf + and Rm constraints. + (atomic_<bare_mnemonic><mode>): Likewise. + (x2): Add vector modes. + (size): Delete. + (bitsize): Add vector modes. + (createpair<mode>): New insn. + (sync_compare_and_swap<mode>): Use ATOMICMODE iterator. Use + createpair<mode> instead of subregs. + (sync_compare_and_swap<mode>_insn): Use ATOMICMODE iterator. Add Rf + and Rm constraints. + (sync_compare_and_swap<mode>_lds_insn): Use ATOMICMODE iterator. Add + Rl constraint. + (atomic_load<mode>): Use ATOMICMODE iterator. Add Rf and Rm + constraints. Make the memory model operand SImode. + (atomic_store<mode>): Likewise. + (atomic_exchange<mode>): Use ATOMICMODE iterator. Add Rf and Rm + constraints. + +2026-10-15 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-10-15 Andrew Stubbs <[email protected]> + Richard Sandiford <[email protected]> + + * doc/rtl.texi: Document MEM_INDEPENDENT_P. + Document new MEM semantics. + * doc/tm.texi: Regenerate. + * emit-rtl.cc (gen_int_mode): Extend to DTRT for vector modes. + (change_address): Split out a static overload with a "validate" + parameter. + (change_address_nv): New. + (adjust_address_1): Permit vectors of addresses. + * emit-rtl.h (change_address_nv): New prototype. + * explow.cc (convert_memory_address_addr_space_1): Permit vectors of + addresses, for no-op conversions only. + * recog.cc (address_operand): Permit vectors of addresses. + * rtl.h (MEM_INDEPENDENT_P): New macro. + (MEM_COPY_ATTRIBUTES): Copy MEM_INDEPENDENT_P. + (get_address_mode): Change return type to machine_mode. + * rtlanal.cc (get_address_mode): Likewise. + * simplify-rtx.cc (simplify_context::simplify_subreg): Handle vectors + of addresses, and simplify subregs of vector mems. + * target.def (pointer_mode): Document vectors of addresses. + (address_mode): Likewise. + (valid_pointer_mode): Change scalar_int_mode to machine_mode, and + document the vector use case. + * targhooks.cc (default_addr_space_valid_pointer_mode): Change + scalar_int_mode to machine_mode, but reject non-scalar inputs. + * targhooks.h (default_addr_space_valid_pointer_mode): Likewise. + +2026-10-15 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-10-15 Andrew Stubbs <[email protected]> + + * config/gcn/constraints.md (RF): Limit to scalar addresses. + (Rf): New. + (Pf): New. + (RL): Limit to scalar addresses. + (Rl): New. + (Pl): New. + (RM): Limit to scalar addresses. + (Rm): New. + (Pm): New. + (RA): New. + * config/gcn/gcn-protos.h (gcn_gen_vector_mem): New prototype. + (gcn_flat_address_p): Add "strict" parameter. + (gcn_global_address_p): Add "data_mode" and "strict" parameters. + (gcn_mode_code_base_reg_class): Delete prototype. + (gcn_scalar_flat_address_p): Add "strict" parameter. + * config/gcn/gcn-valu.md (exec_scatter): Delete define_subst_attr. + (scatter_store): Delete define_subst. + (mov<mode>): Recognize address vectors. Use vector MEMs instead of + gather/scatter. + (*mov<mode>_1reg): Rework from the old "mov<mode>" patterns. Add + memory alternatives. + (*mov<mode>_2reg): Likewise. + (*mov<mode>_4reg): Likewise. + (@mov<mode>_exec): New expander to separate masked loads from others. + (*mov<mode>_1reg_exec): Rework from the old "mov<mode>_exec" patterns. + Add memory alternatives. + (*mov<mode>_2reg_exec): Likewise. + (*mov<mode>_4reg_exec): Likewise. + (load<mode>_exec): New. + (UNSPEC_SGPRBASE define_splits): Split to vector MEMs instead of + gather/scatter unspecs. + (gather_load<mode><vnsi>): Rework to use emit_move_insn. + (gather_load<mode><vndi>): Likewise. + (gather<mode>_expr<exec>): Delete. + (gather<mode>_insn_1offset<exec>): Delete. + (gather<mode>_insn_1offset_ds<exec>): Delete. + (gather<mode>_insn_2offsets<exec>): Delete. + (scatter<mode>_expr<exec_scatter>): Delete. + (scatter<mode>_insn_1offset<exec_scatter>): Delete. + (scatter<mode>_insn_1offset_ds<exec_scatter>): Delete. + (scatter<mode>_insn_2offsets<exec_scatter>): Delete. + (scatter_store<mode><vnsi>): Rework to use emit_move_insn. + (scatter_store<mode><vndi>): Likewise. + (maskload<mode>di): Rework to use mov*_exec. + (maskstore<mode>di): Likewise. + (mask_gather_load<mode><vnsi>): Likewise. + (mask_gather_load<mode><vndi>): Likewise. + (mask_scatter_store<mode><vnsi>): Likewise. + (mask_scatter_store<mode><vndi>): Likewise. + * config/gcn/gcn.cc (single_cst_vector_p): Delete. + (GEN_VNM): Delete gather_expr case. + (gcn_address_register_p): Rename ... + (gcn_scalar_address_register_p): ... to this. + (gcn_vec_address_register_p): Support address vectors. + (gcn_auto_address_register_p): New. + (gcn_flat_address_p): Refactor code from + gcn_addr_space_legitimate_address_p here, and support address vectors. + (gcn_scalar_flat_address_p): Likewise. + (gcn_ds_address_p): Likewise. Add "strict" parameter. Only accept + constant offsets that fit the 16-bit DS offset field. + (gcn_global_address_p): Refactor code from + gcn_addr_space_legitimate_address_p here, and support address vectors, + including vector constant offsets. + (gcn_addr_space_legitimate_address_p): Use the above functions. + Reject vector addresses whose lane count doesn't match the data mode. + Look through SUBREGs when not strict. + (gcn_addr_space_valid_pointer_mode): New. + (gcn_mode_code_base_reg_class): Replace this ... + (gcn_base_reg_class): ... with this. + (gcn_expand_vector_init): Rework using mov*_exec. + (gcn_expand_scalar_to_vector_address): Rework using vector MEM. Set + MEM_INDEPENDENT_P. + (gcn_gen_vector_mem): New. Set MEM_INDEPENDENT_P. + (gcn_secondary_reload): Handle address vectors. + (gcn_valid_move_p): Update calls to gcn_global_address_p. + (move_callee_saved_registers): Rework using mov*_exec. Set + MEM_INDEPENDENT_P. + (print_operand_address): Handle MEM changes. + (print_operand): Likewise. Handle VEC_DUPLICATE offsets. + (TARGET_ADDR_SPACE_VALID_POINTER_MODE): New. + (TARGET_BASE_REG_CLASS): New. + * config/gcn/gcn.h (MODE_CODE_BASE_REG_CLASS): Delete. + * config/gcn/gcn.md (UNSPEC_MASKLOAD): New. + (UNSPEC_GATHER): Delete. + (UNSPEC_SCATTER): Delete. + (*mov<mode>_insn): Disallow MEM to MEM moves. + (*movti_insn): Likewise. + (atomic_fetch_<bare_mnemonic><mode>): Add missing offsets. + (atomic_<bare_mnemonic><mode>): Likewise. + (sync_compare_and_swap<mode>_insn): Likewise. + (atomic_exchange<mode>): Likewise. + +2026-09-28 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-09-25 Andrew Stubbs <[email protected]> + + * config/gcn/gcn-valu.md (mul<mode>3): Remove erroneous hi*hi step. + (mul<mode>3_dup): Likewise. + (mul<mode>3_exec): Likewise. + (mul<mode>3_dup_exec): Likewise. + +2026-09-25 Tobias Burnus <[email protected]> + + Backported from master: + 2026-09-25 Tobias Burnus <[email protected]> + + PR lto/127589 + * lto-streamer-in.cc (lto_input_mode_table): With ACCEL_COMPILER, + check whether found float and int modes are actually enabled/available + at runtime. + +2026-09-24 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-09-24 Andrew Stubbs <[email protected]> + + PR target/127542 + * config/gcn/gcn-valu.md (<expander><mode>2<exec>): Add + "popcount_extra_op". + +2026-09-24 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-09-22 Andrew Stubbs <[email protected]> + + * target.def (base_reg_class): New target hook. + * targhooks.h (default_base_reg_class): Declare. + * targhooks.cc (default_base_reg_class): New function, implementing + the previous BASE_REG_CLASS/MODE_BASE_REG_CLASS/ + MODE_BASE_REG_REG_CLASS/MODE_CODE_BASE_REG_CLASS macro fallback + chain as the hook's default. + * addresses.h (base_reg_class): Rewrite to call the + TARGET_BASE_REG_CLASS hook instead of dispatching through + INSN_BASE_REG_CLASS and the other macros by hand; add a MEM + parameter. + * rtl.h (address_info): Add mem field. + * rtlanal.cc (decompose_mem_address): Set it. + * lra-constraints.cc (simplify_operand_subreg, process_alt_operands, + base_to_reg, base_plus_disp_to_reg, process_address_1, + curr_insn_transform): Pass the enclosing MEM, and INSN where + previously omitted, to base_reg_class. + * reload.cc (find_reloads, find_reloads_address, + find_reloads_address_1, find_reloads_subreg_address): Likewise. + * reload1.cc (maybe_fix_stack_asms): Likewise. + * regcprop.cc: Include target.h. + (replace_oldest_value_addr, replace_oldest_value_mem): Pass MEM to + base_reg_class. + * regrename.cc (base_reg_class_for_rename): Add a MEM parameter. + (scan_rtx_address, scan_rtx): Pass it. + * caller-save.cc: Include target.h. + * config/i386/i386.h (INSN_BASE_REG_CLASS): Delete. + * config/i386/i386-protos.h (ix86_insn_base_reg_class): Delete + declaration. + * config/i386/i386.cc (ix86_insn_base_reg_class): Rename to... + (ix86_base_reg_class): ...this, adjust the signature, and implement + TARGET_BASE_REG_CLASS instead of INSN_BASE_REG_CLASS. + (TARGET_BASE_REG_CLASS): Define. + * doc/tm.texi.in: Add TARGET_BASE_REG_CLASS. Mark BASE_REG_CLASS, + MODE_BASE_REG_CLASS, MODE_BASE_REG_REG_CLASS and + MODE_CODE_BASE_REG_CLASS as obsolete in favor of the new hook, and + remove the now-unused INSN_BASE_REG_CLASS. + * doc/tm.texi: Regenerate. + 2026-09-23 Chung-Lin Tang <[email protected]> Backported from master: @@ -936,4 +1164,4 @@ 2026-07-09 Sandra Loosemore <[email protected]> - * Makefile.in (REVISION_s): Change default message. \ No newline at end of file + * Makefile.in (REVISION_s): Change default message. diff --git a/gcc/DATESTAMP.omp b/gcc/DATESTAMP.omp index 086b6e065352..1e7995319f27 100644 --- a/gcc/DATESTAMP.omp +++ b/gcc/DATESTAMP.omp @@ -1 +1 @@ -20260923 +20261019 diff --git a/gcc/cp/ChangeLog.omp b/gcc/cp/ChangeLog.omp index 2dc8ec18eee2..2be07c63119d 100644 --- a/gcc/cp/ChangeLog.omp +++ b/gcc/cp/ChangeLog.omp @@ -1,3 +1,19 @@ +2026-10-19 Jakub Jelinek <[email protected]> + + Backported from master: + 2026-10-17 Jakub Jelinek <[email protected]> + + PR c++/127559 + * semantics.cc (finish_omp_target_clauses_r): Only record + in local_decls VAR_DECLs, PARM_DECLs and RESULT_DECLs. + For TARGET_EXPR with lambda type mark TARGET_EXPR_SLOT in + local_decls too. Never *walk_subtrees = 0; for lambdas. + Don't add arbitrary expressions of lambda type to + lambda_objects_accessed, only VAR_DECLs, PARM_DECLs or + RESULT_DECLs possibly with COMPONENT_REFs or ARRAY_REFs around + those. If it is handled component case, check in local_decls + the base variable rather than whole expression. + 2026-09-23 Chung-Lin Tang <[email protected]> Backported from master: diff --git a/gcc/testsuite/ChangeLog.omp b/gcc/testsuite/ChangeLog.omp index 8ec1335fcea6..d1bd7fc71983 100644 --- a/gcc/testsuite/ChangeLog.omp +++ b/gcc/testsuite/ChangeLog.omp @@ -1,3 +1,13 @@ +2026-10-14 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-07-09 Andrew Stubbs <[email protected]> + + * gcc.target/gcn/cond_fmaxnm_3.c: Fix assembler scan patterns. + * gcc.target/gcn/cond_fmaxnm_4.c: Fix assembler scan patterns. + * gcc.target/gcn/cond_fminnm_3.c: Fix assembler scan patterns. + * gcc.target/gcn/cond_fminnm_4.c: Fix assembler scan patterns. + 2026-09-23 Chung-Lin Tang <[email protected]> Backported from master: diff --git a/libgomp/ChangeLog.omp b/libgomp/ChangeLog.omp index 1b44f9b5e672..49550e6c9129 100644 --- a/libgomp/ChangeLog.omp +++ b/libgomp/ChangeLog.omp @@ -1,3 +1,24 @@ +2026-10-19 Jakub Jelinek <[email protected]> + + Backported from master: + 2026-10-17 Jakub Jelinek <[email protected]> + + PR c++/127559 + * testsuite/libgomp.c++/target-lambda-5.C: New test. + * testsuite/libgomp.c++/target-lambda-6.C: New test. + +2026-09-25 Tobias Burnus <[email protected]> + + Backported from master: + 2026-09-25 Tobias Burnus <[email protected]> + + PR lto/127589 + * testsuite/libgomp.c/cmplxint-target-1.c: New test. + * testsuite/libgomp.c/cmplxint128-target-1.c: New test. + * testsuite/libgomp.c/dfp-target-1.c: New test. + * testsuite/libgomp.c/float16-target-1.c: New test. + * testsuite/libgomp.c/float16-target-2.c: New test. + 2026-09-23 Tobias Burnus <[email protected]> Backported from master:
