https://gcc.gnu.org/g:1f104578f7c66c397960190f82cdfab85011e5cb
commit 1f104578f7c66c397960190f82cdfab85011e5cb Author: Tobias Burnus <[email protected]> Date: Sun Nov 8 20:57:39 2026 +0100 ChangeLog.omp bump Diff: --- contrib/ChangeLog.omp | 5 + gcc/ChangeLog.omp | 307 +++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP.omp | 2 +- gcc/testsuite/ChangeLog.omp | 311 ++++++++++++++++++++++++++++++++++++++++++++ libgcc/ChangeLog.omp | 8 ++ libgomp/ChangeLog.omp | 36 +++++ 6 files changed, 668 insertions(+), 1 deletion(-) diff --git a/contrib/ChangeLog.omp b/contrib/ChangeLog.omp index 7a26eccefad5..359a28146cf3 100644 --- a/contrib/ChangeLog.omp +++ b/contrib/ChangeLog.omp @@ -1,3 +1,8 @@ +2026-11-08 Tobias Burnus <[email protected]> + + * gcc-changelog/git_update_version.py: Add + 183f71ca629b737344c281 to ignored_commits. + 2026-10-19 Tobias Burnus <[email protected]> * gcc-changelog/git_update_version.py: Add diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp index 51ebce4da1d8..a81e2f7a6e36 100644 --- a/gcc/ChangeLog.omp +++ b/gcc/ChangeLog.omp @@ -1,3 +1,310 @@ +2026-11-06 Andrew Stubbs <[email protected]> + + * config/gcn/gcn.cc (gcn_gimplify_va_arg_expr): Add SIMT support. + +2026-10-30 Paul-Antoine Arras <[email protected]> + + Backported from master: + 2026-10-29 Paul-Antoine Arras <[email protected]> + + * config/gcn/gcn.h (SWITCHABLE_TARGET): Define. + * config/gcn/gcn.cc: Include target-globals.h. + (normal_function_globals, old_is_kernel): New static variables. + (gcn_is_kernel): New function. + (gcn_set_current_function): New function. + (gcn_prepare_pch_save): New function. + (gcn_conditional_register_usage): Use gcn_is_kernel to detect + non-kernel functions and do not require cfun->machine for them. + (TARGET_SET_CURRENT_FUNCTION, TARGET_PREPARE_PCH_SAVE): Define. + +2026-10-30 Andrew Stubbs <[email protected]> + + * config/gcn/gcn-protos.h (gcn_local_decl_alignment): New prototype. + * config/gcn/gcn.cc (GCN_VECTOR_STACK_ALIGNMENT): New define. + (gcn_vector_alignment): New function. + (gcn_local_decl_alignment): New function. + (TARGET_VECTOR_ALIGNMENT): Define. + * config/gcn/gcn.h (LOCAL_DECL_ALIGNMENT): Define. + +2026-10-22 Andrew Stubbs <[email protected]> + + * config/gcn/gcn-tree.cc (struct oacc_attrs): New. + (gcn_goacc_reduction_init): Add SIMT vector reduction case. + (gcn_goacc_reduction_fini): Likewise, using IFN_GOMP_SIMT_REDUCE. + (gcn_goacc_reduction_teardown): Read the worker reduction buffer for + SIMT vector reductions where the vector length is not 64. + (gcn_goacc_reduction): Don't use default_goacc_reduction for vector + reductions. + * config/gcn/gcn.cc (gcn_oacc_dim_size): Return 64 for the vector + dimension in SIMT mode. + * config/gcn/gcn.md (UNSPECV_SIMT_FORK, UNSPECV_SIMT_JOIN): Delete. + (oacc_fork): Emit omp_simt_enter for the vector dimension in SIMT mode. + (oacc_join): Emit omp_simt_exit for the vector dimension in SIMT mode. + (*oacc_fork_insn, *oacc_join_insn): Delete. + (omp_simt_exit): Remove predicate and constraint from operand 0. + (omp_simt_vote_any, omp_simt_xchg_idx): Output "sorry, unimplemented". + +2026-10-21 Andrew Pinski <[email protected]> + + * cfghooks.cc (make_forwarder_block): New data argument, + pass it down to redirect_edge_p. + * cfghooks.h (make_forwarder_block): Add void* argument. + * cfgloop.cc (mfb_reis_set): Remove. + (mfb_redirect_edges_in_set): Add new data argument. + Use it instead of mfb_reis_set. + (form_subloop): Create a local variable instead of + mfb_areis_set. Update call to make_forwarder_block. + (merge_latch_edges): Likewise. + * cfgloopmanip.cc (mfb_kj_edge): Remove. + (mfb_keep_just): Add new data argument. + Use it instead of mfb_kj_edge. + (create_preheader): Use local variable instead of + mfb_kj_edge. Update call to make_forwarder_block. + * cfgloopmanip.h (mfb_keep_just): Add void* argument. + * tree-cfgcleanup.cc (mfb_keep_latches): Add unused void* arugment. + (cleanup_tree_cfg_noloop): Update call to make_forwarder_block. + * tree-ssa-threadupdate.cc + (fwd_jt_path_registry::thread_through_loop_header): Use local + variable instead of mfb_kj_edge. Update call to make_forwarder_block. + +2026-10-21 Andrew Pinski <[email protected]> + + * cfghooks.cc (make_forwarder_block): Remove new_bb_cbk argument. + * cfghooks.h (make_forwarder_block): Remove last argument. + * cfgloop.cc (form_subloop): Update call to make_forwarder_block. + (merge_latch_edges): Likewise. + * cfgloopmanip.cc (create_preheader): Likewise. + * tree-cfgcleanup.cc (cleanup_tree_cfg_noloop): Likewise. + * tree-ssa-threadupdate.cc + (fwd_jt_path_registry::thread_through_loop_header): Likewise. + +2026-10-21 Andrew Stubbs <[email protected]> + + * config/gcn/gcn.md (UNSPECV_SIMT_REDUCE): New unspecv value. + (UNSPEC_SIMT_XCHG_BFLY): Remove. + (SIMT_REDUCE_MODE): New mode iterator. + (omp_simt_xchg_bfly): Delete. + (omp_simt_reduce): New. + (@omp_simt_xchg_bfly<mode>): Delete. + (@omp_simt_reduce<mode>): New. + * config/gcn/gcn-valu.md (V64_SIMT_REDUCE_MODE): New mode iterator. + (omp_simt_xchg_bfly<mode>): Delete. + (omp_simt_reduce<mode>): New. + * config/gcn/gcn-simt-vectorize.cc (pass_gcn_simt_vectorize::execute): + Remove the UNSPEC_SIMT_XCHG_BFLY special case. Add new + UNSPEC_VOLATILE case for UNSPECV_SIMT_REDUCE. + +2026-10-21 Andrew Stubbs <[email protected]> + + * config/nvptx/nvptx-protos.h (nvptx_expand_simt_reduce): New + prototype. + * config/nvptx/nvptx.cc (nvptx_expand_simt_reduce): New function. + * config/nvptx/nvptx.md (omp_simt_xchg_bfly): Delete. + (omp_simt_reduce): New. + * doc/ifn.texi: Delete IFN_GOMP_SIMT_XCHG_BFLY. + Add IFN_GOMP_SIMT_REDUCE. + * internal-fn.def (GOMP_SIMT_XCHG_BFLY): Delete. + (GOMP_SIMT_REDUCE): New. + * internal-fn.cc (expand_GOMP_SIMT_XCHG_BFLY): Delete. + (expand_GOMP_SIMT_REDUCE): New. + * omp-low.cc (lower_rec_input_clauses): Replace + IFN_GOMP_SIMT_XCHG_BFLY algorithm with IFN_GOMP_SIMT_REDUCE call. + Remove the now-unused simt_lane temporary. + * omp-offload.cc (execute_omp_device_lower): Update for the + IFN_GOMP_SIMT_XCHG_BFLY to IFN_GOMP_SIMT_REDUCE change. + * target-insns.def (omp_simt_xchg_bfly): Delete. + (omp_simt_reduce): New. + * tree-cfg.cc (gimple_can_duplicate_bb_p): Update for the + IFN_GOMP_SIMT_XCHG_BFLY to IFN_GOMP_SIMT_REDUCE change. + +2026-10-21 Andrew Stubbs <[email protected]> + + * timevar.def (TV_SIMT): New timevar. + * config/gcn/gcn-simt-vectorize.cc (pass_data_gcn_simt_vectorize): + Use TV_SIMT. + * config/gcn/gcn-simt-cbranch.cc (pass_data_gcn_simt_cbranch): + Likewise. + +2026-10-21 Andrew Stubbs <[email protected]> + + * config.gcc (amdgcn-*-amdhsa): Add gcn-simt-cbranch.o to extra_objs. + * config/gcn/gcn-simt-cbranch.cc: New file. + * config/gcn/gcn-passes.def: Insert pass_gcn_simt_cbranch before + pass_outof_cfg_layout_mode. + * config/gcn/gcn-protos.h (make_pass_gcn_simt_cbranch): New + prototype. + * config/gcn/t-gcn-hsa (gcn-simt-cbranch.o): New rule. + (ALL_HOST_OBJS): Add gcn-simt-cbranch.o. + +2026-10-21 Andrew Stubbs <[email protected]> + + * config.gcc (amdgcn-*-amdhsa): Add gcn-simt-vectorize.o to + extra_objs. + * config/gcn/gcn-passes.def: New file. + * config/gcn/gcn-simt-vectorize.cc: New file. + * config/gcn/gcn-protos.h (make_pass_gcn_simt_vectorize): New + prototype. + * config/gcn/t-gcn-hsa (gcn-simt-vectorize.o): New rule. + (ALL_HOST_OBJS): Add gcn-simt-vectorize.o. + (PASSES_EXTRA): Add config/gcn/gcn-passes.def. + +2026-10-21 Andrew Stubbs <[email protected]> + + * config/gcn/constraints.md (Sa): New register constraint for + AFP_REGS. + * config/gcn/predicates.md (gcn_conditional_register_operand): Accept + DImode condition registers as well as BImode. + * config/gcn/gcn-builtins.def (SIMT_ENTER, SIMT_EXIT): New builtins. + * config/gcn/gcn-protos.h (gcn_output_ensure_scalar): Declare. + * config/gcn/gcn.h: Include gomp-constants.h. + (SCALAR_HARDREG_P, VECTOR_HARDREG_P): New macros. + (struct machine_function): Add vectors_enabled. + * config/gcn/gcn.cc (gcn_init_machine_status): Initialize + vectors_enabled. + (gcn_option_override): Disable variable tracking in SIMT mode. + (gcn_conditional_register_usage): Make EXEC fixed in SIMT mode. + (gcn_function_arg): Pass all arguments in vector registers in SIMT + mode. + (gcn_function_arg_advance): Likewise. + (move_callee_saved_registers_simt): New function. + (move_callee_saved_registers): Use it in SIMT mode. + (gcn_expand_prologue): Mark the addcsi3_scalar_zero insn frame + related, instead of the addsi3_scalar_carry insn, and add a + prologue_use of the stack pointer high part. Initialize EXEC in + kernels in SIMT mode. + (gcn_expand_epilogue): Add a use of EXEC in SIMT mode. + (gcn_expand_builtin_1): Expand GCN_BUILTIN_SIMT_ENTER and + GCN_BUILTIN_SIMT_EXIT. + (gcn_simt_vf): New function. + (gcn_extra_live_on_entry): New function. + (gcn_md_asm_adjust): New function. + (gcn_md_reorg): Skip the EXEC fixup pass in SIMT mode. + (GCN_DEFAULT_VECTORS): Rename to ... + (GCN_DEFAULT_SIMD_VECTORS): ... this. + (GCN_DEFAULT_SIMT_VECTORS): New define. + (gcn_goacc_validate_dims): Honour the OpenACC vector length, up to 64 + lanes, in SIMT mode. + (gcn_fork_join): Keep all fork/join calls in SIMT modes. + (print_operand_address): Assert that the implied zero offset in v1 is + not used in SIMT mode. + (print_operand): Handle EXEC_REG, and invert the condition for VCCZ + and EXECZ. + (gcn_output_ensure_scalar): New function. + (TARGET_EXTRA_LIVE_ON_ENTRY, TARGET_MD_ASM_ADJUST, TARGET_SIMT_VF): + Define. + * config/gcn/gcn.md (LANE_ID_REG): New constant. + (UNSPECV_SIMT_FORK, UNSPECV_SIMT_JOIN, UNSPECV_SIMT_ENTER) + (UNSPECV_SIMT_EXIT, UNSPECV_SIMT_EXEC_BARRIER): New unspecv values. + (UNSPEC_SIMT_XCHG_BFLY, UNSPEC_SIMT_VOTE_ANY, UNSPEC_SIMT_LAST_LANE) + (UNSPEC_SIMT_XCHG_IDX, UNSPEC_VSUBREG_WRITE, UNSPEC_VSUBREG_READ) + (UNSPEC_ENSURE_SCALAR): New unspec values. + (simt, simt_clobber, simt_const, simt_special): New attributes. + (enabled): Take the simt attribute into account. + (*movbi): Add the simt attribute, and use v_readfirstlane_b32 in SIMT + mode. + (*mov<mode>_insn): Likewise, for SISF and QIHI, plus a v_mov_b32 + alternative for scalar-to-vector moves in SIMT mode. + (*mov<mode>_insn): Rename to ... + (mov<mode>_insn): ... this, for DIDF. + (*movti_insn): Rename to ... + (movti_insn): ... this. + (cjump): Set simt_special. + (*cjump_vcc): New insn. + (gcn_simple_call, gcn_indirect_call, gcn_call_value) + (gcn_call_value_indirect, movdi_symbol, cstoresi4) + (cstoredi4_vec_and_scalar, cstoredi4_vector, cstore<mode>4, addsi3) + (adddi3, subsi3, mulsi3, <su>mulsi3_highpart_reg) + (<su>mulsi3_highpart_imm, <su>mulsidi3_imm, muldi3, <expander>si2) + (<expander>di2, <expander>si3, <expander>di3, one_cmpldi2): Set the + new SIMT attributes. + (subdi3): Turn into a define_expand, and clobber a scratch rather + than SCC. + (*subdi3_insn): New insn, split out of subdi3. + (@cselect<mode>): New insn. + (oacc_fork): Expand to UNSPECV_SIMT_FORK in SIMT mode. + (oacc_join): Expand to UNSPECV_SIMT_JOIN in SIMT mode, and keep the + wavefront barrier for the worker dimension only. + (*oacc_fork_insn, *oacc_join_insn, omp_simt_enter, omp_simt_exit) + (omp_simt_lane, omp_simt_xchg_bfly, @omp_simt_xchg_bfly<mode>) + (omp_simt_vote_any, omp_simt_last_lane, omp_simt_xchg_idx) + (@ensure_scalar<mode>, exec_barrier, saveexec, setexec) + (setexec_<expander>, setexec_<expander>_with_save): New patterns. + (execop): New code iterator. + * config/gcn/gcn-valu.md (V64_MOV, V64_MOV_ALT, VSUBREG_ALL) + (VSUBREG_ALT, V64SIDI, V64SIDITI, V64DITI): New mode iterators. + (vec_duplicate<mode><exec>): Disable in SIMT mode until vectors are + enabled, so that the middle-end does not use vectors for memcpy. + (@extract_first_<mode>): New patterns for V_1REG and V_2REG. + (add<mode>3, sub<mode>3): Clobber a scratch rather than VCC. + (<su>mul<vnsi><mode>3): New pattern. + (div_scale<mode><exec_vcc>): Set simt_special. + (vec_cmp<mode>di): Rename to ... + (@vec_cmp<mode>di): ... this, and relax operand 3 to + gcn_alu_operand. + (@vsubreg_write<VSUBREG_ALL:mode><VSUBREG_ALT:mode>) + (@vsubreg_read<VSUBREG_ALL:mode><VSUBREG_ALT:mode>) + (*vsubreg_write<V64_MOV:mode><V64_MOV_ALT:mode>_insn) + (*vsubreg_read<V64_MOV:mode><V64_MOV_ALT:mode>_insn) + (*vsubreg_read<V64_MOV:mode>di_insn): New patterns. + (omp_simt_xchg_bfly<mode>, omp_simt_vote_any_v64si) + (omp_simt_last_lane_v64si, omp_simt_xchg_idx_<mode>): New patterns, + vector counterparts of the corresponding gcn.md patterns. + +2026-10-21 Andrew Stubbs <[email protected]> + + * target.def (TARGET_SIMT_STACK_VARIABLE_PADDING) + (TARGET_SIMT_STACK_VARIABLE_OFFSET): New target hooks. + * doc/tm.texi.in (TARGET_SIMT_STACK_VARIABLE_PADDING) + (TARGET_SIMT_STACK_VARIABLE_OFFSET): Add hook placeholders. + * doc/tm.texi: Regenerate. + * cfgexpand.cc (add_stack_var): Adjust the variable size using + TARGET_SIMT_STACK_VARIABLE_PADDING. + (expand_one_stack_var_at): Offset the variable address using + TARGET_SIMT_STACK_VARIABLE_OFFSET. + (expand_one_stack_var_1): Adjust the variable size using + TARGET_SIMT_STACK_VARIABLE_PADDING. + * expr.cc (emit_push_insn): Offset the destination address using + TARGET_SIMT_STACK_VARIABLE_OFFSET. + * function.cc (assign_parm_find_stack_rtl): Likewise, for incoming + stack parameters. + (locate_and_pad_parm): Adjust the parameter size using + TARGET_SIMT_STACK_VARIABLE_PADDING. + * config/gcn/gcn.cc (gcn_simt_stack_variable_padding): New function. + (gcn_simt_stack_variable_offset): New function. + (TARGET_SIMT_STACK_VARIABLE_PADDING): Define. + (TARGET_SIMT_STACK_VARIABLE_OFFSET): Define. + +2026-10-21 Andrew Stubbs <[email protected]> + + * config/gcn/gcn.opt (msimt): New option. + * config/gcn/gcn.cc (gcn_parse_amdgpu_hsa_kernel_attribute): Diagnose + disagreement between -msimt and --param=offload-gpu-mode. + (gcn_vector_mode_supported_p): Return false in SIMT mode. + (gcn_vectorize_preferred_simd_mode): Return word_mode in SIMT mode. + * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Define __SIMT__ in SIMT + mode. + * config/gcn/mkoffload.cc (main): Detect + --param=offload-gpu-mode=simt* in COLLECT_GCC_OPTIONS, and pass + -msimt to both the offload compiler and the linker. + * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Add msimt. + (MULTILIB_DIRNAMES): Add simt. + +2026-10-21 Andrew Stubbs <[email protected]> + + * doc/params.texi: Document --param=offload-gpu-mode. + * flag-types.h (enum offload_gpu_modes): New type. + * omp-general.cc (omp_max_simt_vf): Do SIMT for amdgcn, optionally. + * params.opt: Add --param=offload-gpu-mode and the enum. + +2026-10-19 Tobias Burnus <[email protected]> + + Backported from master: + 2026-10-19 Tobias Burnus <[email protected]> + + PR middle-end/128001 + * tree.cc (walk_tree_1): Add comment; handle + OMP_METADIRECTIVE explicitly. + 2026-10-21 Andrew Stubbs <[email protected]> * omp-offload.c (oacc_xform_loop): Adjust loop lowering for AMD GCN. diff --git a/gcc/DATESTAMP.omp b/gcc/DATESTAMP.omp index 1e7995319f27..a36a68e157b3 100644 --- a/gcc/DATESTAMP.omp +++ b/gcc/DATESTAMP.omp @@ -1 +1 @@ -20261019 +20261108 diff --git a/gcc/testsuite/ChangeLog.omp b/gcc/testsuite/ChangeLog.omp index d1bd7fc71983..9c449b4949a1 100644 --- a/gcc/testsuite/ChangeLog.omp +++ b/gcc/testsuite/ChangeLog.omp @@ -1,3 +1,314 @@ +2026-10-30 Paul-Antoine Arras <[email protected]> + + Backported from master: + 2026-10-29 Paul-Antoine Arras <[email protected]> + + * gcc.target/gcn/ivopts-reg-budget-1.c: New test. + +2026-10-30 Andrew Stubbs <[email protected]> + + * gcc.target/gcn/simd-array-align-1.c: New test. + * gcc.target/gcn/vector-align-1.c: New test. + +2026-10-21 Andrew Stubbs <[email protected]> + + * lib/target-supports.exp (check_effective_target_amdgcn_simd): New + procedure. + (check_effective_target_amdgcn_simt): New procedure. + (check_effective_target_vect_int): Use + check_effective_target_amdgcn_simd instead of testing for amdgcn + directly, because the vector modes only exist in SIMD mode. + (check_effective_target_vect_early_break): Likewise. + (check_effective_target_vect_early_break_hw): Likewise. + (check_effective_target_vect_intfloat_cvt): Likewise. + (check_effective_target_vect_uintfloat_cvt): Likewise. + (check_effective_target_vect_floatint_cvt): Likewise. + (check_effective_target_vect_floatuint_cvt): Likewise. + (check_effective_target_vect_simd_clones): Likewise. + (check_effective_target_vect_shift): Likewise. + (check_effective_target_whole_vector_shift): Likewise. + (check_effective_target_vect_bswap): Likewise. + (check_effective_target_vect_char_add): Likewise. + (check_effective_target_vect_shift_char): Likewise. + (check_effective_target_vect_long): Likewise. + (check_effective_target_vect_float): Likewise. + (check_effective_target_vect_double): Likewise. + (check_effective_target_vect_long_long): Likewise. + (check_effective_target_vect_perm): Likewise. + (check_effective_target_vect_perm_byte): Likewise. + (check_effective_target_vect_perm_short): Likewise. + (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. + (check_effective_target_vect_widen_mult_hi_to_si): Likewise. + (check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise. + (check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise. + (check_effective_target_vect_pack_trunc): Likewise. + (check_effective_target_vect_unpack): Likewise. + (check_effective_target_vect_hw_misalign): Likewise. + (check_effective_target_vect_natural_alignment): Likewise. + (check_effective_target_vect_fully_masked): Likewise. + (check_effective_target_vect_masked_load): Likewise. + (check_effective_target_vect_masked_store): Likewise. + (check_effective_target_vect_gather_load_ifn): Likewise. + (check_effective_target_vect_scatter_store): Likewise. + (check_effective_target_vect_condition): Likewise. + (check_effective_target_vect_cond_mixed): Likewise. + (check_effective_target_vect_char_mult): Likewise. + (check_effective_target_vect_short_mult): Likewise. + (check_effective_target_vect_int_mult): Likewise. + (check_effective_target_vect_long_mult): Likewise. + (check_effective_target_vect_call_copysignf): Likewise. + (check_effective_target_vect_call_sqrtf): Likewise. + (check_effective_target_vect_call_lrint): Likewise. + (check_effective_target_vect_call_btrunc): Likewise. + (check_effective_target_vect_call_btruncf): Likewise. + (check_effective_target_vect_call_ceil): Likewise. + (check_effective_target_vect_call_ceilf): Likewise. + (check_effective_target_vect_call_floor): Likewise. + (check_effective_target_vect_call_floorf): Likewise. + (check_effective_target_vect_logical_reduc): Likewise. + (check_effective_target_vect_fold_extract_last): Likewise. + (check_vect_support_and_set_flags): Do not run the vectorizer tests + on amdgcn in SIMT mode. + * gcc.target/gcn/avgpr-spill-double.c: Require vect_double. + * gcc.target/gcn/avgpr-spill-int.c: Require vect_int. + * gcc.target/gcn/avgpr-spill-long.c: Likewise. + * gcc.target/gcn/avgpr-spill-short.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_1.c: Require vect_float and vect_double. + * gcc.target/gcn/cond_fmaxnm_1_run.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_2.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_2_run.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_3.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_3_run.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_4.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_4_run.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_5.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_5_run.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_6.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_6_run.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_7.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_7_run.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_8.c: Likewise. + * gcc.target/gcn/cond_fmaxnm_8_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_1.c: Likewise. + * gcc.target/gcn/cond_fminnm_1_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_2.c: Likewise. + * gcc.target/gcn/cond_fminnm_2_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_3.c: Likewise. + * gcc.target/gcn/cond_fminnm_3_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_4.c: Likewise. + * gcc.target/gcn/cond_fminnm_4_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_5.c: Likewise. + * gcc.target/gcn/cond_fminnm_5_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_6.c: Likewise. + * gcc.target/gcn/cond_fminnm_6_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_7.c: Likewise. + * gcc.target/gcn/cond_fminnm_7_run.c: Likewise. + * gcc.target/gcn/cond_fminnm_8.c: Likewise. + * gcc.target/gcn/cond_fminnm_8_run.c: Likewise. + * gcc.target/gcn/cond_shift_3.c: Require vect_int. + * gcc.target/gcn/cond_shift_3_run.c: Likewise. + * gcc.target/gcn/cond_shift_4.c: Likewise. + * gcc.target/gcn/cond_shift_4_run.c: Likewise. + * gcc.target/gcn/cond_shift_8.c: Likewise. + * gcc.target/gcn/cond_shift_8_run.c: Likewise. + * gcc.target/gcn/cond_shift_9.c: Likewise. + * gcc.target/gcn/cond_shift_9_run.c: Likewise. + * gcc.target/gcn/cond_smax_1.c: Likewise. + * gcc.target/gcn/cond_smax_1_run.c: Likewise. + * gcc.target/gcn/cond_smin_1.c: Likewise. + * gcc.target/gcn/cond_smin_1_run.c: Likewise. + * gcc.target/gcn/cond_umax_1.c: Likewise. + * gcc.target/gcn/cond_umax_1_run.c: Likewise. + * gcc.target/gcn/cond_umin_1.c: Likewise. + * gcc.target/gcn/cond_umin_1_run.c: Likewise. + * gcc.target/gcn/math-builtins-1.c: Require vect_float and vect_double. + * gcc.target/gcn/sgpr-spill-double.c: Require amdgcn_simd, and say + why. + * gcc.target/gcn/sgpr-spill-int.c: Likewise. + * gcc.target/gcn/sgpr-spill-long.c: Likewise. + * gcc.target/gcn/sgpr-spill-short.c: Likewise. + * gcc.target/gcn/simd-math-1.c: Require vect_float and vect_double. + * gcc.target/gcn/simd-math-2.c: Likewise. + * gcc.target/gcn/simd-math-3-16.c: Require vect_int. + * gcc.target/gcn/simd-math-3-2.c: Likewise. + * gcc.target/gcn/simd-math-3-32.c: Likewise. + * gcc.target/gcn/simd-math-3-4.c: Likewise. + * gcc.target/gcn/simd-math-3-8.c: Likewise. + * gcc.target/gcn/simd-math-3-char-16.c: Likewise. + * gcc.target/gcn/simd-math-3-char-2.c: Likewise. + * gcc.target/gcn/simd-math-3-char-32.c: Likewise. + * gcc.target/gcn/simd-math-3-char-4.c: Likewise. + * gcc.target/gcn/simd-math-3-char-8.c: Likewise. + * gcc.target/gcn/simd-math-3-char-run-16.c: Likewise. + * gcc.target/gcn/simd-math-3-char-run-2.c: Likewise. + * gcc.target/gcn/simd-math-3-char-run-32.c: Likewise. + * gcc.target/gcn/simd-math-3-char-run-4.c: Likewise. + * gcc.target/gcn/simd-math-3-char-run-8.c: Likewise. + * gcc.target/gcn/simd-math-3-char-run.c: Likewise. + * gcc.target/gcn/simd-math-3-char.c: Likewise. + * gcc.target/gcn/simd-math-3-long-16.c: Likewise. + * gcc.target/gcn/simd-math-3-long-2.c: Likewise. + * gcc.target/gcn/simd-math-3-long-32.c: Likewise. + * gcc.target/gcn/simd-math-3-long-4.c: Likewise. + * gcc.target/gcn/simd-math-3-long-8.c: Likewise. + * gcc.target/gcn/simd-math-3-long-run-16.c: Likewise. + * gcc.target/gcn/simd-math-3-long-run-2.c: Likewise. + * gcc.target/gcn/simd-math-3-long-run-32.c: Likewise. + * gcc.target/gcn/simd-math-3-long-run-4.c: Likewise. + * gcc.target/gcn/simd-math-3-long-run-8.c: Likewise. + * gcc.target/gcn/simd-math-3-long-run.c: Likewise. + * gcc.target/gcn/simd-math-3-long.c: Likewise. + * gcc.target/gcn/simd-math-3-run-16.c: Likewise. + * gcc.target/gcn/simd-math-3-run-2.c: Likewise. + * gcc.target/gcn/simd-math-3-run-32.c: Likewise. + * gcc.target/gcn/simd-math-3-run-4.c: Likewise. + * gcc.target/gcn/simd-math-3-run-8.c: Likewise. + * gcc.target/gcn/simd-math-3-run.c: Likewise. + * gcc.target/gcn/simd-math-3-short-16.c: Likewise. + * gcc.target/gcn/simd-math-3-short-2.c: Likewise. + * gcc.target/gcn/simd-math-3-short-32.c: Likewise. + * gcc.target/gcn/simd-math-3-short-4.c: Likewise. + * gcc.target/gcn/simd-math-3-short-8.c: Likewise. + * gcc.target/gcn/simd-math-3-short-run-16.c: Likewise. + * gcc.target/gcn/simd-math-3-short-run-2.c: Likewise. + * gcc.target/gcn/simd-math-3-short-run-32.c: Likewise. + * gcc.target/gcn/simd-math-3-short-run-4.c: Likewise. + * gcc.target/gcn/simd-math-3-short-run-8.c: Likewise. + * gcc.target/gcn/simd-math-3-short-run.c: Likewise. + * gcc.target/gcn/simd-math-3-short.c: Likewise. + * gcc.target/gcn/simd-math-3.c: Likewise. + * gcc.target/gcn/simd-math-4-char-run.c: Likewise. + * gcc.target/gcn/simd-math-4-char.c: Likewise. + * gcc.target/gcn/simd-math-4-long-run.c: Likewise. + * gcc.target/gcn/simd-math-4-long.c: Likewise. + * gcc.target/gcn/simd-math-4-run.c: Likewise. + * gcc.target/gcn/simd-math-4-short-run.c: Likewise. + * gcc.target/gcn/simd-math-4-short.c: Likewise. + * gcc.target/gcn/simd-math-4.c: Likewise. + * gcc.target/gcn/simd-math-5-16.c: Likewise. + * gcc.target/gcn/simd-math-5-32.c: Likewise. + * gcc.target/gcn/simd-math-5-4.c: Likewise. + * gcc.target/gcn/simd-math-5-8.c: Likewise. + * gcc.target/gcn/simd-math-5-char-16.c: Likewise. + * gcc.target/gcn/simd-math-5-char-32.c: Likewise. + * gcc.target/gcn/simd-math-5-char-4.c: Likewise. + * gcc.target/gcn/simd-math-5-char-8.c: Likewise. + * gcc.target/gcn/simd-math-5-char-run-16.c: Likewise. + * gcc.target/gcn/simd-math-5-char-run-32.c: Likewise. + * gcc.target/gcn/simd-math-5-char-run-4.c: Likewise. + * gcc.target/gcn/simd-math-5-char-run-8.c: Likewise. + * gcc.target/gcn/simd-math-5-char-run.c: Likewise. + * gcc.target/gcn/simd-math-5-char.c: Likewise. + * gcc.target/gcn/simd-math-5-long-16.c: Likewise. + * gcc.target/gcn/simd-math-5-long-32.c: Likewise. + * gcc.target/gcn/simd-math-5-long-4.c: Likewise. + * gcc.target/gcn/simd-math-5-long-8.c: Likewise. + * gcc.target/gcn/simd-math-5-long-run-16.c: Likewise. + * gcc.target/gcn/simd-math-5-long-run-32.c: Likewise. + * gcc.target/gcn/simd-math-5-long-run-4.c: Likewise. + * gcc.target/gcn/simd-math-5-long-run-8.c: Likewise. + * gcc.target/gcn/simd-math-5-long-run.c: Likewise. + * gcc.target/gcn/simd-math-5-long.c: Likewise. + * gcc.target/gcn/simd-math-5-run-16.c: Likewise. + * gcc.target/gcn/simd-math-5-run-32.c: Likewise. + * gcc.target/gcn/simd-math-5-run-4.c: Likewise. + * gcc.target/gcn/simd-math-5-run-8.c: Likewise. + * gcc.target/gcn/simd-math-5-run.c: Likewise. + * gcc.target/gcn/simd-math-5-short-16.c: Likewise. + * gcc.target/gcn/simd-math-5-short-32.c: Likewise. + * gcc.target/gcn/simd-math-5-short-4.c: Likewise. + * gcc.target/gcn/simd-math-5-short-8.c: Likewise. + * gcc.target/gcn/simd-math-5-short-run-16.c: Likewise. + * gcc.target/gcn/simd-math-5-short-run-32.c: Likewise. + * gcc.target/gcn/simd-math-5-short-run-4.c: Likewise. + * gcc.target/gcn/simd-math-5-short-run-8.c: Likewise. + * gcc.target/gcn/simd-math-5-short-run.c: Likewise. + * gcc.target/gcn/simd-math-5-short.c: Likewise. + * gcc.target/gcn/simd-math-5.c: Likewise. + * gcc.target/gcn/smax_1.c: Likewise. + * gcc.target/gcn/smax_1_run.c: Likewise. + * gcc.target/gcn/smin_1.c: Likewise. + * gcc.target/gcn/smin_1_run.c: Likewise. + * gcc.target/gcn/sram-ecc-3.c: Likewise. + * gcc.target/gcn/sram-ecc-4.c: Likewise. + * gcc.target/gcn/sram-ecc-7.c: Likewise. + * gcc.target/gcn/sram-ecc-8.c: Likewise. + * gcc.target/gcn/umax_1.c: Likewise. + * gcc.target/gcn/umax_1_run.c: Likewise. + * gcc.target/gcn/umin_1.c: Likewise. + * gcc.target/gcn/umin_1_run.c: Likewise. + * gcc.target/gcn/vcc-clobber.c: Likewise. + +2026-10-21 Andrew Stubbs <[email protected]> + + * gcc.target/gcn/simt-cond-1.c: New test. + * gcc.target/gcn/simt-cond-1b.c: Likewise. + * gcc.target/gcn/simt-cond-2.c: Likewise. + * gcc.target/gcn/simt-cond-2b.c: Likewise. + * gcc.target/gcn/simt-cond-3.c: Likewise. + * gcc.target/gcn/simt-cond-3b.c: Likewise. + * gcc.target/gcn/simt-cond-4.c: Likewise. + * gcc.target/gcn/simt-cond-4b.c: Likewise. + * gcc.target/gcn/simt-cond-5.c: Likewise. + * gcc.target/gcn/simt-cond-5b.c: Likewise. + * gcc.target/gcn/simt-cond-6.c: Likewise. + * gcc.target/gcn/simt-cond-6b.c: Likewise. + * gcc.target/gcn/simt-cond-7.c: Likewise. + * gcc.target/gcn/simt-cond-7b.c: Likewise. + * gcc.target/gcn/simt-cond-8.c: Likewise. + * gcc.target/gcn/simt-cond-8b.c: Likewise. + * gcc.target/gcn/simt-cond-9.c: Likewise. + * gcc.target/gcn/simt-cond-9b.c: Likewise. + * gcc.target/gcn/simt-cond-10.c: Likewise. + * gcc.target/gcn/simt-cond-10b.c: Likewise. + * gcc.target/gcn/simt-cond-11.c: Likewise. + * gcc.target/gcn/simt-cond-11b.c: Likewise. + * gcc.target/gcn/simt-cond-12.c: Likewise. + * gcc.target/gcn/simt-cond-12b.c: Likewise. + * gcc.target/gcn/simt-cond-13.c: Likewise. + * gcc.target/gcn/simt-cond-13b.c: Likewise. + * gcc.target/gcn/simt-cond-14.c: Likewise. + * gcc.target/gcn/simt-cond-14b.c: Likewise. + * gcc.target/gcn/simt-cond-15.c: Likewise. + * gcc.target/gcn/simt-cond-15b.c: Likewise. + * gcc.target/gcn/simt-cond-16.c: Likewise. + * gcc.target/gcn/simt-cond-17.c: Likewise. + * gcc.target/gcn/simt-cond-18.c: Likewise. + +2026-10-21 Andrew Stubbs <[email protected]> + + * gcc.target/gcn/simt-ensure-scalar-1.c: New test. + * gcc.target/gcn/simt-stackparams-1.c: Likewise. + * gcc.target/gcn/simt-stackparams-2.c: Likewise. + * gcc.target/gcn/simt-stackparams-3.c: Likewise. + * gcc.target/gcn/simt-stackvar-1.c: Likewise. + * gcc.target/gcn/simt-stackvar-2.c: Likewise. + * gcc.target/gcn/simt-stackvar-3.c: Likewise. + +2026-10-21 Andrew Stubbs <[email protected]> + + * gcc.target/gcn/simt-asm-g-1.c: New test, checking that a "g" asm + operand can hold a per-lane value in SIMT mode. + * gcc.target/gcn/simt-asm-r-1.c: New test, likewise for an "r" asm + operand. + * gcc.target/gcn/simt-avgpr-spill-int.c: New test, checking that + spills inside a SIMT region go to the AVGPRs rather than through + v_readlane. + * gcc.target/gcn/simt-avgpr-spill-double.c: New test. + * gcc.target/gcn/simt-avgpr-spill-long.c: New test. + * gcc.target/gcn/simt-avgpr-spill-short.c: New test. + * gcc.target/gcn/simt-avgpr-spill-run.c: New test, checking that the + values spilled by simt-avgpr-spill-int.c keep their per-lane values + across a spill/reload. + +2026-10-19 Tobias Burnus <[email protected]> + + Backported from master: + 2026-10-19 Tobias Burnus <[email protected]> + + PR middle-end/128001 + * gfortran.dg/gomp/metadirective-14.f90: New test. + 2026-10-14 Andrew Stubbs <[email protected]> Backported from master: diff --git a/libgcc/ChangeLog.omp b/libgcc/ChangeLog.omp new file mode 100644 index 000000000000..48aacd8af5d8 --- /dev/null +++ b/libgcc/ChangeLog.omp @@ -0,0 +1,8 @@ +2026-10-21 Andrew Stubbs <[email protected]> + + * config/gcn/amdgcn_veclib.h: Do not define anything when __SIMT__ is + defined. + * config/gcn/lib2-vec_divmod-di.c: Likewise. + * config/gcn/lib2-vec_divmod-hi.c: Likewise. + * config/gcn/lib2-vec_divmod-qi.c: Likewise. + * config/gcn/lib2-vec_divmod.c: Likewise. \ No newline at end of file diff --git a/libgomp/ChangeLog.omp b/libgomp/ChangeLog.omp index 49550e6c9129..514174a7e509 100644 --- a/libgomp/ChangeLog.omp +++ b/libgomp/ChangeLog.omp @@ -1,3 +1,39 @@ +2026-11-08 Arsen Arsenović <[email protected]> + + Backported from master: + 2026-11-07 Arsen Arsenović <[email protected]> + + * plugin/plugin-gcn.c (allocate_session_kernargs): Use + 'kernargs_size' instead of 'sizeof (struct kernargs)'. + * testsuite/libgomp.c-c++-common/kernel-launch-many-vars.c: New test. + +2026-10-30 Andrew Stubbs <[email protected]> + + * libgomp.texi (AMD Radeon (GCN)): Document stack size rounding. + * plugin/plugin-gcn.c (init_environment_variables): Round stack_size + up to an odd multiple of 4 kiB. + +2026-10-30 Andrew Stubbs <[email protected]> + + Backported from master: + 2026-10-29 Andrew Stubbs <[email protected]> + + * plugin/plugin-gcn.c (drain_queue): Execute placeholder entries + with the queue lock held. + +2026-10-22 Andrew Stubbs <[email protected]> + + * testsuite/libgomp.c-c++-common/simt-reduction-amdgcn-1.c: New test. + * testsuite/libgomp.c-c++-common/simt-reduction-amdgcn-2.c: New test. + * testsuite/libgomp.oacc-c-c++-common/simt-reduction-amdgcn-1.c: New + test. + * testsuite/libgomp.oacc-c-c++-common/simt-reduction-amdgcn-2.c: New + test. + +2026-10-21 Andrew Stubbs <[email protected]> + + * libgomp.h (team_malloc): Add SIMT variant of the asm. + 2026-10-19 Jakub Jelinek <[email protected]> Backported from master:
