On 32-bit x86, register class CLOBBERED_REGS is a proper subset of
LEGACY_REGS, which causes IRA not to consider it separately for register
allocation, even when it has lower cost than other classes. This patch is
useful to fix code generation problem that appears with no-PLT PIC tailcalls.
Was there a specific reason for CLOBBERED_REGS class to be listed as late as
it is? On 32-bit this class contains only EAX, ECX, EDX.
OK?
* config/i386/i386.h (enum reg_class): Move CLOBBERED_REGS before
Q_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 1e755d3..75071ac 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1300,17 +1300,17 @@ extern const char *host_detect_local_cpu (int argc,
const char **argv);
enum reg_class
{
NO_REGS,
AREG, DREG, CREG, BREG, SIREG, DIREG,
AD_REGS, /* %eax/%edx for DImode */
+ CLOBBERED_REGS, /* call-clobbered integer registers */
Q_REGS, /* %eax %ebx %ecx %edx */
NON_Q_REGS, /* %esi %edi %ebp %esp */
INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
- CLOBBERED_REGS, /* call-clobbered integer registers */
GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp
%esp
%r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
FLOAT_REGS,
SSE_FIRST_REG,
NO_REX_SSE_REGS,
@@ -1361,16 +1361,16 @@ enum reg_class
#define REG_CLASS_NAMES \
{ "NO_REGS", \
"AREG", "DREG", "CREG", "BREG", \
"SIREG", "DIREG", \
"AD_REGS", \
+ "CLOBBERED_REGS", \
"Q_REGS", "NON_Q_REGS", \
"INDEX_REGS", \
"LEGACY_REGS", \
- "CLOBBERED_REGS", \
"GENERAL_REGS", \
"FP_TOP_REG", "FP_SECOND_REG", \
"FLOAT_REGS", \
"SSE_FIRST_REG", \
"NO_REX_SSE_REGS", \
"SSE_REGS", \
@@ -1400,17 +1400,17 @@ enum reg_class
{ 0x02, 0x0, 0x0 }, /* DREG */ \
{ 0x04, 0x0, 0x0 }, /* CREG */ \
{ 0x08, 0x0, 0x0 }, /* BREG */ \
{ 0x10, 0x0, 0x0 }, /* SIREG */ \
{ 0x20, 0x0, 0x0 }, /* DIREG */ \
{ 0x03, 0x0, 0x0 }, /* AD_REGS */ \
+ { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
{ 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
{ 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \
{ 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
{ 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
- { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
{ 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
{ 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
{ 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
{ 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \
