Messages by Thread
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[PATCH] vect: Do not try to duplicate_and_interleave one-element mode.
Robin Dapp
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[PATCH][PR116569] match.pd: Check trunc_mod vector obtap before folding.
Jennifer Schmitz
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[r15-3509 Regression] FAIL: gcc.target/i386/pr88531-2c.c scan-assembler-times vmulps 1 on Linux/x86_64
haochen.jiang
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[PATCH v3] GCC Driver : Enable very long gcc command-line option
Deepthi . Hemraj
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[PATCH]middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store recognition [PR116628]
Tamar Christina
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[PATCH] match: Change (A * B) + (-C) to (B - C/A) * A, if C multiple of A [PR109393]
konstantinos . eleftheriou
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[PATCH] x86-64: Don't use temp for argument in a TImode register
H.J. Lu
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[PATCH] Fix SLP double-reduction support
Richard Biener
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[PATCH] c++, v2: Implement for static locals CWG 2867 - Order of initialization for structured bindings [PR115769]
Jakub Jelinek
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[PATCH v2 0/9] SMALL code model fixes, optimization fixes, LTO and minimal C++ enablement
Evgeny Karpov
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[PATCH] c++: Properly mangle CONST_DECL without a INTEGER_CST value [PR116511]
Simon Martin
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[PATCH] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.
Jin Ma
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New Ukrainian PO file for 'gcc' (version 14.2.0)
Translation Project Robot
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[PATCH] RISC-V: Add more vector-vector extract cases.
Robin Dapp
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[patch,reload] PR116326: Add #define IN_RELOAD1_CC
Georg-Johann Lay
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[PATCH] ada: Fix gcc-interface/misc.cc compilation on SPARC
Rainer Orth
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[PATCH] fab: Factor out the main folding part of pass_fold_builtins::execute [PR116601]
Andrew Pinski
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[PATCH] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for xtheadvector
Jin Ma
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Re: [PATCH] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for xtheadvector
Xi Ruoyao
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Re: [PATCH] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for xtheadvector
Jin Ma
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[PATCH v2] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector
Jin Ma
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Re: [PATCH v2] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector
钟居哲
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Re: [PATCH v2] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector
Jin Ma
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[PATCH v3] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector
Jin Ma
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Re: [PATCH v3] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector
钟居哲
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Re: [PATCH v3] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector
Jin Ma
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[PATCH v4] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector
Jin Ma
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Re: [PATCH v4] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector
钟居哲
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Re: [PATCH v4] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector
Jeff Law
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[PATCH] gimple ssa: Don't use __builtin_popcount in switch exp transform [PR116616]
Filip Kastl
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[PATCH v3 2/2] [APX CFCMOV] Support APX CFCMOV in backend
Kong, Lingling
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[PATCH v3 1/2] [APX CFCMOV] Support APX CFCMOV in if_convert pass
Kong, Lingling
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[r15-3498 Regression] FAIL: gcc.target/i386/pr59539-1.c scan-assembler-times vmovdqu|vmovups 1 on Linux/x86_64
haochen.jiang
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[PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model
Zhao Dingyi
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[PATCH] doc: Enhance Intel CPU documentation
Haochen Jiang
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[PATCH] Git ignores .vscode
YunQiang Su
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[PATCH] c++: ICE with structured bindings and m-d array [PR102594]
Marek Polacek
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[PATCH RFA] libstdc++: -Wswitch and ios::openmode
Jason Merrill
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[PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements
Raphael Moreira Zinsly
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[PATCH] Fortran: fix ICE in gfc_create_module_variable [PR100273]
Harald Anlauf
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[PATCH] RISC-V: Define LOGICAL_OP_NON_SHORT_CIRCUIT to 1 [PR116615]
Palmer Dabbelt
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[PATCH] c++: vtable referring to "unavailable" virtual fn [PR116606]
Marek Polacek
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[to-be-committed][V2][RISC-V] Avoid unnecessary extensions after sCC insns
Jeff Law
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[pushed] doc: remove stray character
Marek Polacek
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Re: [PATCH 6/8] gcn: Add else operand to masked loads.
Andrew Stubbs
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[PATCH] arm: avoid indirect sibcalls when IP is live [PR116597]
Richard Earnshaw
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[PATCH] testsuite/gcc.dg/pr84877.c: Add machinery to stabilize stack aligmnent
Hans-Peter Nilsson
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[PATCH] c++: Fix mangling of otherwise unattached class-scope lambdas [PR116568]
Nathaniel Shead
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[PATCH] c++: template depth of lambda in default targ [PR116567]
Patrick Palka
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[RISCV] target-specific source placement
Nathan Sidwell
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[PATCH 2/3] tree-optimization/116610 - wrong SLP induction bias for mask peeling
Richard Biener
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[PATCH 3/3] Handle non-grouped stores as single-lane SLP
Richard Biener
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[PATCH 1/3] tree-optimization/116609 - SLP live lane vectorization with partial vectors
Richard Biener
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[RFC PATCH] c++: Add alignas further test coverage [PR110345]
Jakub Jelinek
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c++: Add no_unique_address attribute further test coverage [PR110345]
Jakub Jelinek
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c++: Add noreturn attribute further test coverage [PR110345]
Jakub Jelinek
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c++: Add nodiscard attribute further test coverage [PR110345]
Jakub Jelinek
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Re: [committed][nvptx] Use .alias directive for mptx >= 6.3
Thomas Schwinge
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Fix 'gcc.target/nvptx/alias-2.c' comment (was: [committed][nvptx] Use .alias directive for mptx >= 6.3)
Thomas Schwinge
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Move from 'gcc.target/nvptx/nvptx.exp' into 'target-supports.exp' additions for nvptx target (was: [PATCH] Make 'target-supports.exp' additions for nvptx target generally available)
Thomas Schwinge
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Zen5 tuning part 5: update instruction latencies in x86-tune-costs
Jan Hubicka
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[PATCH v2 1/2] Genmatch: Support control flow graph case 1 for phi on condition
pan2 . li
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[PATCH] RISC-V: Fix out of index in riscv_select_multilib_by_abi
YunQiang Su
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[PATCH V4 10/10] autovectorizer: Test autovectorization of different dot-prod modes.
Victor Do Nascimento
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[PATCH V4 04/10] arm: Fix arm backend-use of (u|s|us)dot_prod patterns
Victor Do Nascimento
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[PATCH] libsanitizer: On aarch64 use hint #34 in prologue of libsanitizer functions
Jakub Jelinek
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[PATCH] [AARCH64] adjust gcc.target/aarch64/sve/mask_gather_load_7.c
Richard Biener