Please, ignore the previous patch. This is the intended patch.
Sorry.
--
Evandro Menezes
On 11/04/2015 05:18 PM, Evandro Menezes wrote:
This patch adds extra tuning information about AArch64 targets:
* Maximum number of case values before resorting to a jump table
The default values assumed independently of the specific backends
may be rather low for modern processors, which sport quite efficient
direct branch prediction, whereas indirect branch prediction is
still typically not so efficient. This value may be specifically
set for a processor or left at zero to use the default values.
* L1 cache line size
The auto-prefetcher uses this information when emitting software
prefetch insns.
Please, commit if it's alright.
Thank you,
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 81792bc..ecf4685 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -195,6 +195,9 @@ struct tune_params
int vec_reassoc_width;
int min_div_recip_mul_sf;
int min_div_recip_mul_df;
+ int max_case_values; /* Case values threshold; or 0 for the default. */
+
+ int cache_line_size; /* Cache line size; or 0 for the default. */
/* An enum specifying how to take into account CPU autoprefetch capabilities
during instruction scheduling:
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5c8604f..e7f1c07 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -355,6 +355,8 @@ static const struct tune_params generic_tunings =
1, /* vec_reassoc_width. */
2, /* min_div_recip_mul_sf. */
2, /* min_div_recip_mul_df. */
+ 0, /* max_case_values. */
+ 0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */
(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
};
@@ -378,6 +380,8 @@ static const struct tune_params cortexa53_tunings =
1, /* vec_reassoc_width. */
2, /* min_div_recip_mul_sf. */
2, /* min_div_recip_mul_df. */
+ 0, /* max_case_values. */
+ 0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
};
@@ -401,6 +405,8 @@ static const struct tune_params cortexa57_tunings =
1, /* vec_reassoc_width. */
2, /* min_div_recip_mul_sf. */
2, /* min_div_recip_mul_df. */
+ 0, /* max_case_values. */
+ 0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
(AARCH64_EXTRA_TUNE_RENAME_FMA_REGS) /* tune_flags. */
};
@@ -424,6 +430,8 @@ static const struct tune_params cortexa72_tunings =
1, /* vec_reassoc_width. */
2, /* min_div_recip_mul_sf. */
2, /* min_div_recip_mul_df. */
+ 0, /* max_case_values. */
+ 0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */
(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
};
@@ -446,6 +454,8 @@ static const struct tune_params thunderx_tunings =
1, /* vec_reassoc_width. */
2, /* min_div_recip_mul_sf. */
2, /* min_div_recip_mul_df. */
+ 0, /* max_case_values. */
+ 0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */
(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
};
@@ -468,6 +478,8 @@ static const struct tune_params xgene1_tunings =
1, /* vec_reassoc_width. */
2, /* min_div_recip_mul_sf. */
2, /* min_div_recip_mul_df. */
+ 0, /* max_case_values. */
+ 0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */
(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
};
@@ -3242,6 +3254,20 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return aarch64_tls_referenced_p (x);
}
+/* Implement TARGET_CASE_VALUES_THRESHOLD. */
+
+static unsigned int
+aarch64_case_values_threshold (void)
+{
+ /* Use the specified limit for the number of cases before using jump
+ tables at higher optimization levels. */
+ if (optimize > 2
+ && selected_cpu->tune->max_case_values != 0)
+ return selected_cpu->tune->max_case_values;
+ else
+ return default_case_values_threshold ();
+}
+
/* Return true if register REGNO is a valid index register.
STRICT_P is true if REG_OK_STRICT is in effect. */
@@ -7672,6 +7698,13 @@ aarch64_override_options_internal (struct gcc_options *opts)
opts->x_param_values,
global_options_set.x_param_values);
+ /* Set the L1 cache line size. */
+ if (selected_cpu->tune->cache_line_size != 0)
+ maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
+ selected_cpu->tune->cache_line_size,
+ opts->x_param_values,
+ global_options_set.x_param_values);
+
aarch64_override_options_after_change_1 (opts);
}
@@ -13385,6 +13418,7 @@ aarch64_promoted_type (const_tree t)
return float_type_node;
return NULL_TREE;
}
+
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST aarch64_address_cost
@@ -13432,6 +13466,9 @@ aarch64_promoted_type (const_tree t)
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
+#undef TARGET_CASE_VALUES_THRESHOLD
+#define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
+
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
