On 07/04/16 15:51, Kyrill Tkachov wrote: > Hi all, > > In this wrong-code PR we have a Thumb2 peephole transforming: > tst r3, #2 > bne .L3 > beq .L6 > > into: > lsls r3, r3, #30 // LSLS is shorter than TST in Thumb2 > bmi .L3 > beq .L6 > > that is, the branch following the extract+compare has its condition > properly changed but the > following branch doesn't get updated to check the opposite condition of > MI (PL). > Since the peepholes in thumb2.md only see the compare and a single > branch the solution, > suggested by Richard, is to guard those peepholes on the condition that > the condition register > is dead after the first branch. This patch does that and with it we no > longer perform the transformation > on the testcase. I've checked manually that we still perform the > peephole when the condition register > is indeed dead after the sequence. > > Bootstrapped and tested on on arm-none-linux-gnueabihf with > --with-mode=thumb as this affects only > Thumb2 codegen. > > Ok for trunk? > > This PR also affects GCC 5 and 4.9 so I'll be testing the patch there as > well. > > Thanks, > Kyrill > > > 2016-04-07 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/70566 > * config/arm/thumb2.md (tst + branch-> lsls + branch > peephole below *orsi_not_shiftsi_si): Require that condition > register is dead after the peephole. > (second peephole after the above): Likewise. > > 2016-04-07 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/70566 > * gcc.c-torture/execute/pr70566.c: New test.
OK. R.
