On Thu, May 11, 2017 at 12:28:56PM -0600, Jeff Law wrote:
> On 05/10/2017 01:05 PM, Uros Bizjak wrote:
> > On Wed, May 10, 2017 at 5:18 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
> > > On Wed, May 10, 2017 at 4:27 PM, Jakub Jelinek <ja...@redhat.com> wrote:
> > > > On Tue, May 09, 2017 at 06:06:47PM +0200, Uros Bizjak wrote:
> > > > > Attached patch enables post-reload compare elimination pass by
> > > > > providing expected patterns (duplicates of existing patterns with
> > > > > setters of reg and flags switched in the parallel) for flag setting
> > > > > arithmetic instructions.
> > > > >
> > > > > The merge triggers more than 3000 times during the gcc bootstrap,
> > > > > mostly in cases where intervening memory load or store prevents
> > > > > combine from merging the arithmetic insn and the following compare.
> > > > >
> > > > > Also, some recent linux x86_64 defconfig build results in ~200 merges,
> > > > > removing ~200 test/cmp insns. Not much, but I think the results still
> > > > > warrant the pass to be enabled.
> > > >
> > > > Isn't the right fix instead to change the compare-elim.c pass to either
> > > > accept both reg vs. flags orderings in parallel, or both depending
> > > > on some target hook, or change it to the order i386.md and most other
> > > > major targets use and just fix up mn10300/rx (and aarch64?) to use the
> > > > same
> > > > order?
> >
> > Attached patch changes compare-elim.c order to what i386.md expects.
> >
> > Thoughts?
> Haven't looked at the patch itself. But I do have the necessary bits to
> convert the mn103 port. It was slightly more than just fixing the md file,
> but nothing significant or time consuming. The net result is 100% identical
> code for newlib before your patch vs after your patch w/mn103 converted.
>
> Hell, it was easy enough, I'll take a cut at the rx port.
I have completely untested patch for both, here is what I came up with:
--- gcc/config/mn10300/mn10300.md.jj 2017-01-01 12:45:40.000000000 +0100
+++ gcc/config/mn10300/mn10300.md 2017-05-11 20:12:52.685388632 +0200
@@ -592,12 +592,12 @@ (define_insn "addsi3"
;; Note that ADD IMM,SP does not set the flags, so omit that here.
(define_insn "*addsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,!r")
- (plus:SI (match_operand:SI 1 "register_operand" "%0, r")
- (match_operand:SI 2 "nonmemory_operand" "ri, r")))
- (set (reg CC_REG)
- (compare (plus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (plus:SI (match_operand:SI 1 "register_operand" "%0, r")
+ (match_operand:SI 2 "nonmemory_operand" "ri, r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,!r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
{ return mn10300_output_add (operands, true); }
[(set_attr "timings" "11,22")]
@@ -605,12 +605,13 @@ (define_insn "*addsi3_flags"
;; A helper to expand the above, with the CC_MODE filled in.
(define_expand "addsi3_flags"
- [(parallel [(set (match_operand:SI 0 "register_operand")
- (plus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "nonmemory_operand")))
- (set (reg:CCZNC CC_REG)
- (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])]
+ [(parallel [(set (reg:CCZNC CC_REG)
+ (compare:CCZNC
+ (plus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand")
+ (plus:SI (match_dup 1) (match_dup 2)))])]
""
)
@@ -791,12 +792,12 @@ (define_insn "subsi3"
)
(define_insn "*subsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r, r")
- (minus:SI (match_operand:SI 1 "register_operand" "0, r")
- (match_operand:SI 2 "nonmemory_operand" "ri,r")))
- (set (reg CC_REG)
- (compare (minus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0, r")
+ (match_operand:SI 2 "nonmemory_operand" "ri,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r, r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
"@
sub %2,%0
@@ -807,12 +808,13 @@ (define_insn "*subsi3_flags"
;; A helper to expand the above, with the CC_MODE filled in.
(define_expand "subsi3_flags"
- [(parallel [(set (match_operand:SI 0 "register_operand")
- (minus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "nonmemory_operand")))
- (set (reg:CCZNC CC_REG)
- (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])]
+ [(parallel [(set (reg:CCZNC CC_REG)
+ (compare:CCZNC
+ (minus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand")
+ (minus:SI (match_dup 1) (match_dup 2)))])]
""
)
@@ -1195,12 +1197,12 @@ (define_insn "andsi3"
)
(define_insn "*andsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=D,D,r")
- (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
- (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
- (set (reg CC_REG)
- (compare (and:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D,D,r")
+ (and:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"@
and %2,%0
@@ -1282,12 +1284,12 @@ (define_insn "iorsi3"
)
(define_insn "*iorsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=D,D,r")
- (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
- (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
- (set (reg CC_REG)
- (compare (ior:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D,D,r")
+ (ior:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"@
or %2,%0
@@ -1318,12 +1320,12 @@ (define_insn "xorsi3"
)
(define_insn "*xorsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=D,D,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
- (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
- (set (reg CC_REG)
- (compare (xor:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D,D,r")
+ (xor:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"@
xor %2,%0
@@ -1346,11 +1348,11 @@ (define_insn "one_cmplsi2"
)
(define_insn "*one_cmplsi2_flags"
- [(set (match_operand:SI 0 "register_operand" "=D")
- (not:SI (match_operand:SI 1 "register_operand" " 0")))
- (set (reg CC_REG)
- (compare (not:SI (match_dup 1))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (not:SI (match_operand:SI 1 "register_operand" " 0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D")
+ (not:SI (match_dup 1)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"not %0"
)
--- gcc/config/rx/rx.md.jj 2017-01-01 12:45:42.000000000 +0100
+++ gcc/config/rx/rx.md 2017-05-11 20:37:59.815063239 +0200
@@ -843,11 +843,11 @@ (define_insn "abssi2"
)
(define_insn "*abssi2_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (abs:SI (match_operand:SI 1 "register_operand" "0,r")))
- (set (reg CC_REG)
- (compare (abs:SI (match_dup 1))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (abs:SI (match_operand:SI 1 "register_operand" "0,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (abs:SI (match_dup 1)))]
;; Note - although the ABS instruction does set the O bit in the processor
;; status word, it does not do so in a way that is comparable with the CMP
;; instruction. Hence we use CC_ZSmode rather than CC_ZSOmode.
@@ -897,12 +897,12 @@ (define_insn "addsi3_internal"
)
(define_insn "*addsi3_flags"
- [(set (match_operand:SI 0 "register_operand"
"=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
- (plus:SI (match_operand:SI 1 "register_operand"
"%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
- (match_operand:SI 2 "rx_source_operand"
"r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
- (set (reg CC_REG)
- (compare (plus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (plus:SI (match_operand:SI 1 "register_operand"
"%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
+ (match_operand:SI 2 "rx_source_operand"
"r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand"
"=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
"@
add\t%2, %0
@@ -925,12 +925,13 @@ (define_insn "*addsi3_flags"
;; A helper to expand the above with the CC_MODE filled in.
(define_expand "addsi3_flags"
- [(parallel [(set (match_operand:SI 0 "register_operand")
- (plus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "rx_source_operand")))
- (set (reg:CC_ZSC CC_REG)
- (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])]
+ [(parallel [(set (reg:CC_ZSC CC_REG)
+ (compare:CC_ZSC
+ (plus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "rx_source_operand"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand")
+ (plus:SI (match_dup 1) (match_dup 2)))])]
)
(define_insn "adc_internal"
@@ -948,20 +949,20 @@ (define_insn "adc_internal"
)
(define_insn "*adc_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (plus:SI
- (plus:SI
- (ltu:SI (reg:CC CC_REG) (const_int 0))
- (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
- (match_operand:SI 2 "rx_source_operand"
"r,Sint08,Sint16,Sint24,i,Q")))
- (set (reg CC_REG)
- (compare
+ [(set (reg CC_REG)
+ (compare
(plus:SI
(plus:SI
(ltu:SI (reg:CC CC_REG) (const_int 0))
- (match_dup 1))
- (match_dup 2))
- (const_int 0)))]
+ (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
+ (match_operand:SI 2 "rx_source_operand"
"r,Sint08,Sint16,Sint24,i,Q"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
+ (plus:SI
+ (plus:SI
+ (ltu:SI (reg:CC CC_REG) (const_int 0))
+ (match_dup 1))
+ (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
"adc\t%2, %0"
[(set_attr "timings" "11,11,11,11,11,33")
@@ -969,36 +970,36 @@ (define_insn "*adc_flags"
)
;; Peepholes to match:
-;; (set (reg A) (reg B))
;; (set (CC) (compare:CC (reg A/reg B) (const_int 0)))
+;; (set (reg A) (reg B))
;; and replace them with the addsi3_flags pattern, using an add
;; of zero to copy the register and set the condition code bits.
(define_peephole2
- [(set (match_operand:SI 0 "register_operand")
- (match_operand:SI 1 "register_operand"))
- (set (reg:CC CC_REG)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- ""
- [(parallel [(set (match_dup 0)
- (plus:SI (match_dup 1) (const_int 0)))
- (set (reg:CC_ZSC CC_REG)
+ [(set (reg:CC CC_REG)
+ (compare:CC (match_operand:SI 0 "register_operand")
+ (const_int 0)))
+ (set (match_dup 0)
+ (match_operand:SI 1 "register_operand"))]
+ ""
+ [(parallel [(set (reg:CC_ZSC CC_REG)
(compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
- (const_int 0)))])]
+ (const_int 0)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 1) (const_int 0)))])]
)
(define_peephole2
- [(set (match_operand:SI 0 "register_operand")
- (match_operand:SI 1 "register_operand"))
- (set (reg:CC CC_REG)
- (compare:CC (match_dup 1)
- (const_int 0)))]
- ""
- [(parallel [(set (match_dup 0)
- (plus:SI (match_dup 1) (const_int 0)))
- (set (reg:CC_ZSC CC_REG)
+ [(set (reg:CC CC_REG)
+ (compare:CC (match_operand:SI 1 "register_operand")
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand")
+ (match_dup 1))]
+ ""
+ [(parallel [(set (reg:CC_ZSC CC_REG)
(compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
- (const_int 0)))])]
+ (const_int 0)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 1) (const_int 0)))])]
)
(define_expand "adddi3"
@@ -1109,12 +1110,12 @@ (define_insn "andsi3"
)
(define_insn "*andsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
- (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
- (match_operand:SI 2 "rx_source_operand"
"r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
- (set (reg CC_REG)
- (compare (and:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (and:SI (match_operand:SI 1 "register_operand"
"%0,0,0,0,0,0,r,r,0")
+ (match_operand:SI 2 "rx_source_operand"
"r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand"
"=r,r,r,r,r,r,r,r,r")
+ (and:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
and\t%2, %0
@@ -1341,11 +1342,11 @@ (define_insn "negsi2"
;; Note that the O and C flags are not set as per a normal compare,
;; and thus are unusable in that context.
(define_insn "*negsi2_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (neg:SI (match_operand:SI 1 "register_operand" "0,r")))
- (set (reg CC_REG)
- (compare (neg:SI (match_dup 1))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (neg:SI (match_operand:SI 1 "register_operand" "0,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (neg:SI (match_dup 1)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
neg\t%0
@@ -1365,11 +1366,11 @@ (define_insn "one_cmplsi2"
)
(define_insn "*one_cmplsi2_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (not:SI (match_operand:SI 1 "register_operand" "0,r")))
- (set (reg CC_REG)
- (compare (not:SI (match_dup 1))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (not:SI (match_operand:SI 1 "register_operand" "0,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (not:SI (match_dup 1)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
not\t%0
@@ -1398,12 +1399,12 @@ (define_insn "iorsi3"
)
(define_insn "*iorsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
- (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
- (match_operand:SI 2 "rx_source_operand"
"r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
- (set (reg CC_REG)
- (compare (ior:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (ior:SI (match_operand:SI 1 "register_operand"
"%0,0,0,0,0,0,r,r,0")
+ (match_operand:SI 2 "rx_source_operand"
"r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand"
"=r,r,r,r,r,r,r,r,r")
+ (ior:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
or\t%2, %0
@@ -1430,12 +1431,12 @@ (define_insn "rotlsi3"
)
(define_insn "*rotlsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (rotate:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "rx_shift_operand" "rn")))
- (set (reg CC_REG)
- (compare (rotate:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (rotate:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "rx_shift_operand" "rn"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"rotl\t%2, %0"
[(set_attr "length" "3")]
@@ -1452,12 +1453,12 @@ (define_insn "rotrsi3"
)
(define_insn "*rotrsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (rotatert:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "rx_shift_operand" "rn")))
- (set (reg CC_REG)
- (compare (rotatert:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (rotatert:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "rx_shift_operand" "rn"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (rotatert:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"rotr\t%2, %0"
[(set_attr "length" "3")]
@@ -1477,12 +1478,12 @@ (define_insn "ashrsi3"
)
(define_insn "*ashrsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
- (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
- (set (reg CC_REG)
- (compare (ashiftrt:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
+ (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (ashiftrt:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
shar\t%2, %0
@@ -1505,12 +1506,12 @@ (define_insn "lshrsi3"
)
(define_insn "*lshrsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
- (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
- (set (reg CC_REG)
- (compare (lshiftrt:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
+ (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (lshiftrt:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
shlr\t%2, %0
@@ -1533,12 +1534,12 @@ (define_insn "ashlsi3"
)
(define_insn "*ashlsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
- (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
- (set (reg CC_REG)
- (compare (ashift:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
+ (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (ashift:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
shll\t%2, %0
@@ -1556,12 +1557,12 @@ (define_insn_and_split "ssaddsi3"
""
"#"
"reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:SI (match_dup 1) (match_dup 2)))
- (set (reg:CC_ZSC CC_REG)
+ [(parallel [(set (reg:CC_ZSC CC_REG)
(compare:CC_ZSC
(plus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])
+ (const_int 0)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
(unspec:SI [(match_dup 0) (reg:CC CC_REG)]
UNSPEC_BUILTIN_SAT))]
@@ -1597,12 +1598,12 @@ (define_insn "subsi3"
;; Note that the O flag is set as if (compare op1 op2) not for
;; what is described here, (compare op0 0).
(define_insn "*subsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
- (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
- (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
- (set (reg CC_REG)
- (compare (minus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
+ (match_operand:SI 2 "rx_source_operand"
"r,Uint04,n,r,Q"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
"@
sub\t%2, %0
@@ -1616,12 +1617,13 @@ (define_insn "*subsi3_flags"
;; A helper to expand the above with the CC_MODE filled in.
(define_expand "subsi3_flags"
- [(parallel [(set (match_operand:SI 0 "register_operand")
- (minus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "rx_source_operand")))
- (set (reg:CC_ZSC CC_REG)
- (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])]
+ [(parallel [(set (reg:CC_ZSC CC_REG)
+ (compare:CC_ZSC
+ (minus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "rx_source_operand"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand")
+ (minus:SI (match_dup 1) (match_dup 2)))])]
)
(define_insn "sbb_internal"
@@ -1639,18 +1641,18 @@ (define_insn "sbb_internal"
)
(define_insn "*sbb_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (minus:SI
- (minus:SI
- (match_operand:SI 1 "register_operand" " 0,0")
- (match_operand:SI 2 "rx_compare_operand" " r,Q"))
- (geu:SI (reg:CC CC_REG) (const_int 0))))
- (set (reg CC_REG)
+ [(set (reg CC_REG)
(compare
(minus:SI
- (minus:SI (match_dup 1) (match_dup 2))
+ (minus:SI
+ (match_operand:SI 1 "register_operand" " 0,0")
+ (match_operand:SI 2 "rx_compare_operand" " r,Q"))
(geu:SI (reg:CC CC_REG) (const_int 0)))
- (const_int 0)))]
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (minus:SI
+ (minus:SI (match_dup 1) (match_dup 2))
+ (geu:SI (reg:CC CC_REG) (const_int 0))))]
"reload_completed"
"sbb\t%2, %0"
[(set_attr "timings" "11,33")
@@ -1710,13 +1712,13 @@ (define_insn "xorsi3"
)
(define_insn "*xorsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
- (match_operand:SI 2 "rx_source_operand"
- "r,Sint08,Sint16,Sint24,i,Q")))
- (set (reg CC_REG)
- (compare (xor:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
+ (match_operand:SI 2 "rx_source_operand"
+ "r,Sint08,Sint16,Sint24,i,Q"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
+ (xor:SI (match_dup 1) (match_dup 2)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"xor\t%Q2, %0"
[(set_attr "timings" "11,11,11,11,11,33")
Jakub
