On Fri, Oct 27, 2017 at 02:22:39PM +0100, Richard Sandiford wrote: > This patch replaces switch statements that call specific generator > functions with code that constructs the rtl pattern directly. > This seemed to scale better to SVE and also seems less error-prone. > > As a side-effect, the patch fixes the REV handling for diff==1, > vmode==E_V4HFmode and adds missing support for diff==3, > vmode==E_V4HFmode. > > To compensate for the lack of switches that check for specific modes, > the patch makes aarch64_expand_vec_perm_const_1 reject permutes on > single-element vectors (specifically V1DImode).
OK. Would you mind placing a comment somewhere near both the unspecs, and the patterns using these unspecs to warn that the calls constructing the RTX here *MUST* be kept in sync? Some of these patterns are probably used rarely enough that we could easily miss an unreconizable insn. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > > 2017-10-27 Richard Sandiford <richard.sandif...@linaro.org> > Alan Hayward <alan.hayw...@arm.com> > David Sherwood <david.sherw...@arm.com> > > gcc/ > * config/aarch64/aarch64.c (aarch64_evpc_trn, aarch64_evpc_uzp) > (aarch64_evpc_zip, aarch64_evpc_ext, aarch64_evpc_rev) > (aarch64_evpc_dup): Generate rtl direcly, rather than using > named expanders. > (aarch64_expand_vec_perm_const_1): Explicitly check for permutes > of a single element. >
