On Fri, 02 Mar 2018 16:27:41 PST (-0800), Jim Wilson wrote:
On 03/01/2018 01:26 PM, Palmer Dabbelt wrote:
+@item -mrelax
+@itemx -mno-relax
+Take advantage of linker relaxations to reduce the number of instructions
+required to materalize symbol addresses.
materalize->materialize
This is not just number of instructions, it is also code size, since
linker relaxation can convert non-compressed instructions into
compressed instructions.
Also, this isn't clear which option is the default. If you look at the
other options descriptions, I tried to make it clear which was the
default when there was more than one choice. I don't think you should
rely on @item or @itemx to define which is the default.
Thanks. How does this look?
commit e7c570f37384d824cb9725f237920e9691e57269
gpg: Signature made Tue 06 Mar 2018 04:52:46 PM PST
gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
gpg: issuer "pal...@dabbelt.com"
gpg: Good signature from "Palmer Dabbelt <pal...@dabbelt.com>" [ultimate]
gpg: aka "Palmer Dabbelt <pal...@sifive.com>" [ultimate]
Author: Palmer Dabbelt <pal...@sifive.com>
Date: Thu Mar 1 12:01:06 2018 -0800
RISC-V: Add and document the "-mno-relax" option
RISC-V relies on aggressive linker relaxation to get good code size. As
a result no text symbol addresses can be known until link time, which
means that alignment must be handled during the link. This alignment
pass is essentially just another linker relaxation, so this has the
unfortunate side effect that linker relaxation is required for
correctness on many RISC-V targets.
The RISC-V assembler has supported an ".option norelax" for a long time
because there are situations in which linker relaxation is a bad idea --
the canonical example is when trying to materialize the initial value of
the global pointer into a register, which would otherwise be relaxed to
a NOP. We've been relying on users who want to disable relaxation for
an entire link to pass "-Wl,--no-relax", but that still relies on the
linker relaxing R_RISCV_ALIGN to handle alignment despite it not being
strictly necessary.
This patch adds a GCC option, "-mno-relax", that disable linker
relaxation by adding ".option norelax" to the top of every generated
assembly file. The assembler is smart enough to handle alignment at
assemble time for files that have never emitted a relaxable relocation,
so this is sufficient to really disable all relaxations in the linker,
which results in significantly faster link times for large objects.
This also has the side effect of allowing toolchains that don't support
linker relaxation (LLVM and the Linux module loader) to function
correctly. Toolchains that don't support linker relaxation should
default to "-mno-relax" and error when presented with any R_RISCV_ALIGN
relocation as those need to be handled for correctness.
gcc/ChangeLog
2018-03-01 Palmer Dabbelt <pal...@sifive.com>
* config/riscv/riscv.opt (mrelax): New option.
* config/riscv/riscv.c (riscv_file_start): Emit ".option
"norelax" when riscv_mrelax is disabled.
* doc/invoke.texi (RISC-V): Document "-mrelax" and "-mno-relax".
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index c38f6c394d54..3e81874de232 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3979,6 +3979,11 @@ riscv_file_start (void)
/* Instruct GAS to generate position-[in]dependent code. */
fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no"));
+
+ /* If the user specifies "-mno-relax" on the command line then disable linker
+ relaxation in the assembler. */
+ if (! riscv_mrelax)
+ fprintf (asm_out_file, "\t.option norelax\n");
}
/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 581a26bb5c1e..b37ac75d9bb4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -106,6 +106,11 @@ mexplicit-relocs
Target Report Mask(EXPLICIT_RELOCS)
Use %reloc() operators, rather than assembly macros, to load addresses.
+mrelax
+Target Bool Var(riscv_mrelax) Init(1)
+Take advantage of linker relaxations to reduce the number of instructions
+required to materialize symbol addresses.
+
Mask(64BIT)
Mask(MUL)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8d366c626bae..deb48af2ecad 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1042,7 +1042,8 @@ See RS/6000 and PowerPC Options.
-msave-restore -mno-save-restore @gol
-mstrict-align -mno-strict-align @gol
-mcmodel=medlow -mcmodel=medany @gol
--mexplicit-relocs -mno-explicit-relocs @gol}
+-mexplicit-relocs -mno-explicit-relocs @gol
+-mrelax -mno-relax @gol}
@emph{RL78 Options}
@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol
@@ -23102,6 +23103,12 @@ Use or do not use assembler relocation operators when
dealing with symbolic
addresses. The alternative is to use assembler macros instead, which may
limit optimization.
+@item -mrelax
+@itemx -mno-relax
+Take advantage of linker relaxations to reduce the number of instructions
+required to materialize symbol addresses. The default is to take advantage of
+linker relaxations.
+
@end table
@node RL78 Options
