On 2/9/19, H.J. Lu <hjl.to...@gmail.com> wrote: >> >> Hm, this is a bit worrying, we don't want to introduce ABI >> >> incompatibilites w.r.t. alignment. We still need to be ABI compatible >> >> for MMX values and emit unaligned loads/stores when necessary. >> > >> > We need to audit all usages of SSE_REG_MODE_P and VALID_SSE2_REG_MODE. >> > And I don't think we should put DI and SI in them. >> >> Perhaps we should leave SSE_REG_MODE_P and VALID_SSE2_REG_MODE as they >> are and ammend usage sites with e.g. (TARGET_MMX_WITH_SSE && >> VALID_MMX_REG_MODE (...))? This is much more fine-grained comparing to > > Not VALID_MMX_REG_MODE since it includes SI/DI, but not V2SF. > We only want 8-byte vector modes here.
Well, I'm not forcing VALID_MMX_REG_MODE here, it is just an example; the important part is in the addition of (TARGET_MMX_WITH_SSE && some_modes). Surely, we don't want to align SImode to 128 bits in ALIGN_MODE_128. Uros. >> a big-hammer approach of changing wide-used defines like >> SSE_REG_MODE_P and VALID_SSE2_REG_MODE. As an example, >> ix86_hard_regno_mode_ok already includes all MMX modes for SSE_REG_P, >> while mentioned ALIGN_MODE_128 would be wrong when SSE_REG_MODE_P is >> changed. > > I will give it a try. > > -- > H.J. >
