On Sat, Feb 9, 2019 at 10:41 AM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> On 2/9/19, H.J. Lu <hjl.to...@gmail.com> wrote:
> >> >> Hm, this is a bit worrying, we don't want to introduce ABI
> >> >> incompatibilites w.r.t. alignment. We still need to be ABI compatible
> >> >> for MMX values and emit unaligned loads/stores when necessary.
> >> >
> >> > We need to audit all usages of SSE_REG_MODE_P and VALID_SSE2_REG_MODE.
> >> > And I don't think we should put DI and SI in them.
> >>
> >> Perhaps we should leave SSE_REG_MODE_P and VALID_SSE2_REG_MODE as they
> >> are and ammend usage sites with e.g. (TARGET_MMX_WITH_SSE &&
> >> VALID_MMX_REG_MODE (...))? This is much more fine-grained comparing to
> >
> > Not VALID_MMX_REG_MODE since it includes SI/DI, but not V2SF.
> > We only want 8-byte vector modes here.
>
> Well, I'm not forcing VALID_MMX_REG_MODE here, it is just an example;
> the important part is in the addition of (TARGET_MMX_WITH_SSE &&
> some_modes). Surely, we don't want to align SImode to 128 bits in
> ALIGN_MODE_128.
>
I am testing this.
--
H.J.
From 1a3a4c4d2e133d99c6671788a8475efe39804dbb Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.to...@gmail.com>
Date: Thu, 24 Jan 2019 08:27:41 -0800
Subject: [PATCH] i386: Allow 64-bit vector modes in SSE registers
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support 64-bit vectors.
PR target/89021
* config/i386/i386.c (ix86_set_reg_reg_cost): Also support
VALID_MMX_WITH_SSE_REG_MODE.
(ix86_vector_mode_supported_p): Likewise.
* config/i386/i386.h (TARGET_MMX_WITH_SSE): New.
(TARGET_MMX_WITH_SSE_P): Likewise.
(VALID_MMX_WITH_SSE_REG_MODE): Likewise.
---
gcc/config/i386/i386.c | 3 +++
gcc/config/i386/i386.h | 14 ++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 12bc7926f86..ba02c26c8b2 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -40235,6 +40235,7 @@ ix86_set_reg_reg_cost (machine_mode mode)
|| (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
|| (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
|| (TARGET_SSE && VALID_SSE_REG_MODE (mode))
+ || (TARGET_MMX_WITH_SSE && VALID_MMX_WITH_SSE_REG_MODE (mode))
|| (TARGET_MMX && VALID_MMX_REG_MODE (mode)))
units = GET_MODE_SIZE (mode);
}
@@ -44057,6 +44058,8 @@ ix86_vector_mode_supported_p (machine_mode mode)
return true;
if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
return true;
+ if (TARGET_MMX_WITH_SSE && VALID_MMX_WITH_SSE_REG_MODE (mode))
+ return true;
if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
return true;
if (TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode))
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 83b025e0cf5..f75fd426293 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -201,6 +201,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_16BIT TARGET_CODE16
#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
+/* In 64-bit mode, SSE2 can be used to emulate MMX instructions.
+ FIXME: All 3DNOW patterns needs to be updated with SSE emulation. */
+#define TARGET_MMX_WITH_SSE \
+ (TARGET_64BIT && TARGET_SSE2 && !TARGET_3DNOW)
+#define TARGET_MMX_WITH_SSE_P(x) \
+ (TARGET_64BIT_P (x) && TARGET_SSE2_P (x) && !TARGET_3DNOW_P (x))
+
#include "config/vxworks-dummy.h"
#include "config/i386/i386-opts.h"
@@ -1143,6 +1150,13 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|| (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
|| (MODE) == TFmode || (MODE) == V1TImode)
+/* NB: Don't use VALID_MMX_REG_MODE with TARGET_MMX_WITH_SSE since we
+ want to include 8-byte vector modes, like V2SFmode, but not DImode
+ nor SImode. */
+#define VALID_MMX_WITH_SSE_REG_MODE(MODE) \
+ ((MODE) == V1DImode || (MODE) == V8QImode || (MODE) == V4HImode \
+ || (MODE) == V2SImode || (MODE) == V2SFmode)
+
#define VALID_SSE2_REG_MODE(MODE) \
((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
|| (MODE) == V2DImode || (MODE) == DFmode)
--
2.20.1
