Przemyslaw Wirkus <przemyslaw.wir...@arm.com> writes:
> @@ -5234,21 +5234,21 @@ (define_insn_and_rewrite "*cond_sub<mode>_3_const"
>
> ;; Predicated floating-point subtraction from a constant, merging with an
> ;; independent value.
> -(define_insn_and_rewrite "*cond_sub<mode>_any_const"
> +;; The subtraction predicate and the merge predicate are allowed to be
> +;; different.
Sorry for the micromanagement, but I think this is easier to read if it
flows as a single paragraph:
;; Predicated floating-point subtraction from a constant, merging with an
;; independent value. The subtraction predicate and the merge predicate are
;; allowed to be different.
or is written as two separate paragraphs:
;; Predicated floating-point subtraction from a constant, merging with an
;; independent value.
;;
;; The subtraction predicate and the merge predicate are allowed to be
;; different.
Same for the second comment.
> @@ -5271,6 +5271,41 @@ (define_insn_and_rewrite "*cond_sub<mode>_any_const"
> [(set_attr "movprfx" "yes")]
> )
>
> +;; Predicated floating-point subtraction from a constant, merging with an
> +;; independent value.
> +;; The subtraction predicate and the merge predicate must be the same.
> +(define_insn_and_rewrite "*cond_sub<mode>_strict_const"
> + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w")
> + (unspec:SVE_FULL_F
> + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
> + (unspec:SVE_FULL_F
> + [(match_dup 1)
> + (const_int SVE_STRICT_GP)
> + (match_operand:SVE_FULL_F 2 "aarch64_sve_float_arith_immediate")
> + (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")]
> + UNSPEC_COND_FSUB)
> + (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")]
> + UNSPEC_SEL))]
> + "TARGET_SVE && !rtx_equal_p (operands[3], operands[4])"
> + "@
> + movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m,
> %0.<Vetype>, #%2
> + movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m,
> %0.<Vetype>, #%2
> + #"
> + "&& 1"
> + {
> + if (reload_completed
> + && register_operand (operands[4], <MODE>mode)
> + && !rtx_equal_p (operands[0], operands[4]))
> + {
> + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3],
> + operands[4], operands[1]));
> + operands[4] = operands[3] = operands[0];
> + }
> + else
> + FAIL;
I should have realised this would be the case, sorry, but now that there's
only one rewrite, this should simply be:
"&& reload_completed
&& register_operand (operands[4], <MODE>mode)
&& !rtx_equal_p (operands[0], operands[4]))"
{
emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3],
operands[4], operands[1]));
operands[4] = operands[3] = operands[0];
}
OK with those changes, thanks.
Richard
