Hi Segher,
Thanks for the review!
on 2020/12/15 上午2:51, Segher Boessenkool wrote:
> Hi!
>
> On Wed, Dec 02, 2020 at 05:44:24PM +0800, Kewen.Lin wrote:
>> This patch is to use paradoxical subreg instead of
>> zero_extend for promoting QI/HI to SI/DI when we
>> want to construct one vector with these modes.
>> Since we do the gpr->vsx movement and vector merge
>> or pack later, the high part is useless and safe to
>> use paradoxical subreg. It can avoid useless rlwinms
>> generated for signed cases.
>
>> --- a/gcc/config/rs6000/rs6000.c
>> +++ b/gcc/config/rs6000/rs6000.c
>> @@ -6793,17 +6793,8 @@ rs6000_expand_vector_init (rtx target, rtx vals)
>> /* Force the values into word_mode registers. */
>> for (i = 0; i < n_elts; i++)
>> {
>> - rtx tmp = force_reg (GET_MODE_INNER (mode), XVECEXP (vals, 0, i));
>> - if (TARGET_POWERPC64)
>> - {
>> - op[i] = gen_reg_rtx (DImode);
>> - emit_insn (gen_zero_extendqidi2 (op[i], tmp));
>> - }
>> - else
>> - {
>> - op[i] = gen_reg_rtx (SImode);
>> - emit_insn (gen_zero_extendqisi2 (op[i], tmp));
>> - }
>> + rtx tmp = force_reg (inner_mode, XVECEXP (vals, 0, i));
>> + op[i] = simplify_gen_subreg (Pmode, tmp, inner_mode, 0);
>> }
>
> Pmode is defined based on TARGET_64BIT, not TARGET_POWERPC64.
>
Good point, you are right, is it ok to change this part with one
explicit mode based on TARGET_POWERPC64?
rtx tmp = force_reg (inner_mode, XVECEXP (vals, 0, i));
machine_mode tmode = TARGET_POWERPC64 ? DImode : SImode;
op[i] = simplify_gen_subreg (tmode, tmp, inner_mode, 0);
> But, can you not always use SImode here?
>
Sorry that I didn't quite follow here.
It uses DImode when TARGET_POWERPC64, so not SImode always (when
!TARGET_POWERPC64).
BR,
Kewen
