UNSPEC_SI_FROM_SF is not supported for -m32 caused ICE on P8BE-32bit,
since P8 Vector and above doesn't have fast mechanism to move SFmode to
SImode for m32, don't generate IFN VEC_SET for it.
Tested pass on P8BE/LE {m32,m64}.
gcc/ChangeLog:
2021-03-24 Xionghu Luo <luo...@linux.ibm.com>
* config/rs6000/predicates.md (vec_set_index_operand): New
predicate.
* config/rs6000/vector.md: Use vec_set_index_operand.
---
gcc/config/rs6000/predicates.md | 6 ++++++
gcc/config/rs6000/vector.md | 3 +--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 859af75dfbd..51184390d24 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1940,3 +1940,9 @@ (define_predicate "d_form_memory"
return !indexed_address (addr, mode);
})
+
+;; Return true if m64 on p8v and above for vec_set with variable index.
+(define_predicate "vec_set_index_operand"
+ (if_then_else (match_test "TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT")
+ (match_operand 0 "reg_or_cint_operand")
+ (match_operand 0 "const_int_operand")))
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index e5191bd1424..c9ed5adfa4c 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -1227,7 +1227,7 @@ (define_expand "vec_init<mode><VEC_base_l>"
(define_expand "vec_set<mode>"
[(match_operand:VEC_E 0 "vlogical_operand")
(match_operand:<VEC_base> 1 "register_operand")
- (match_operand 2 "reg_or_cint_operand")]
+ (match_operand 2 "vec_set_index_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_set (operands[0], operands[1], operands[2]);
@@ -1505,7 +1505,6 @@ (define_expand "vashr<mode>3"
; is to allow us to use a code iterator, but not completely list all of the
; vector rotates, etc. to prevent canonicalization
-
(define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
[(match_operand:<VEC_base> 0 "register_operand")
(VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
--
2.25.1
