There's no masked vpandw or vpandb, similar for vpxor/vpor/vpandn. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} Ready to push to trunk.
gcc/ChangeLog: * config/i386/sse.md (<sse2_avx2>_andnot<mode>3_mask): Removed. (<sse>_andnot<mode>3<mask_name>): Disable V*HFmode patterns for mask_applied. (<code><mode>3<mask_name>): Ditto. (*<code><mode>3<mask_name>): Ditto. (VFB_128_256): Adjust condition of V8HF/V16HFmode according to real instruction. (VFB_512): Ditto. --- gcc/config/i386/sse.md | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1f9c496e7c0..92640aecc41 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -340,8 +340,7 @@ (define_mode_iterator VF_128_256 ;; 128- and 256-bit float vector modes for bitwise operations (define_mode_iterator VFB_128_256 - [(V16HF "TARGET_AVX512FP16") - (V8HF "TARGET_AVX512FP16") + [(V16HF "TARGET_AVX") (V8HF "TARGET_SSE2") (V8SF "TARGET_AVX") V4SF (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) @@ -399,7 +398,7 @@ (define_mode_iterator VF_512 ;; All 512bit vector float modes for bitwise operations (define_mode_iterator VFB_512 - [(V32HF "TARGET_AVX512FP16") V16SF V8DF]) + [V32HF V16SF V8DF]) (define_mode_iterator VI48_AVX512VL [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") @@ -4581,7 +4580,8 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" (not:VFB_128_256 (match_operand:VFB_128_256 1 "register_operand" "0,x,v,v")) (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] - "TARGET_SSE && <mask_avx512vl_condition>" + "TARGET_SSE && <mask_avx512vl_condition> + && (!<mask_applied> || <ssescalarmode>mode != HFmode)" { char buf[128]; const char *ops; @@ -4648,7 +4648,7 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" (not:VFB_512 (match_operand:VFB_512 1 "register_operand" "v")) (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F" + "TARGET_AVX512F && (!<mask_applied> || <ssescalarmode>mode != HFmode)" { char buf[128]; const char *ops; @@ -4683,7 +4683,8 @@ (define_expand "<code><mode>3<mask_name>" (any_logic:VFB_128_256 (match_operand:VFB_128_256 1 "vector_operand") (match_operand:VFB_128_256 2 "vector_operand")))] - "TARGET_SSE && <mask_avx512vl_condition>" + "TARGET_SSE && <mask_avx512vl_condition> + && (!<mask_applied> || <ssescalarmode>mode != HFmode)" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_expand "<code><mode>3<mask_name>" @@ -4691,7 +4692,7 @@ (define_expand "<code><mode>3<mask_name>" (any_logic:VFB_512 (match_operand:VFB_512 1 "nonimmediate_operand") (match_operand:VFB_512 2 "nonimmediate_operand")))] - "TARGET_AVX512F" + "TARGET_AVX512F && (!<mask_applied> || <ssescalarmode>mode != HFmode)" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*<code><mode>3<mask_name>" @@ -4700,6 +4701,7 @@ (define_insn "*<code><mode>3<mask_name>" (match_operand:VFB_128_256 1 "vector_operand" "%0,x,v,v") (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] "TARGET_SSE && <mask_avx512vl_condition> + && (!<mask_applied> || <ssescalarmode>mode != HFmode) && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { char buf[128]; @@ -4766,7 +4768,8 @@ (define_insn "*<code><mode>3<mask_name>" (any_logic:VFB_512 (match_operand:VFB_512 1 "nonimmediate_operand" "%v") (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2])) + && (!<mask_applied> || <ssescalarmode>mode != HFmode)" { char buf[128]; const char *ops; @@ -16738,17 +16741,6 @@ (define_expand "<sse2_avx2>_andnot<mode>3_mask" (match_operand:<avx512fmaskmode> 4 "register_operand")))] "TARGET_AVX512F") -(define_expand "<sse2_avx2>_andnot<mode>3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL - (and:VI12_AVX512VL - (not:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand")) - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand") - (match_operand:<avx512fmaskmode> 4 "register_operand")))] - "TARGET_AVX512BW") - (define_insn "*andnot<mode>3" [(set (match_operand:VI 0 "register_operand" "=x,x,v") (and:VI -- 2.18.1