[PATCH,RS6000 5/5] Replace MASK_<xxxx> usage with OPTION_MASK_<xxxx>
This continues the changes of replacing the MASK_<xxxx> defines
with their OPTION_MASK_<xxxx> equivalents.
This patch removes the defines for
MASK_P8_VECTOR, MASK_P9_VECTOR, MASK_P9_MISC, MASK_POPCNTB,
MASK_POPCNTD, MASK_PPC_GFXOPT, MASK_PPC_GPOPT, MASK_RECIP_PRECISION,
MASK_SOFT_FLOAT, MASK_VSX, MASK_POWER10, MASK_P10_FUSION.
gcc/
* config/rs6000/aix71.h (MASK_PPC_GPOPT, MASK_PPC_GFXOPT): Replace with
OPTION_MASK_PPC_GPOPT, OPTION_MASK_PPC_GFXOPT.
* config/rs6000/darwin.h (MASK_PPC_GFXOPT): Replace with
OPTION_MASK_PPC_GFXOPT.
* config/rs6000/darwin64-biarch.h (MASK_PPC_GFXOPT): Same.
* config/rs6000/default64.h (MASK_PPC_GPOPT, MASK_PPC_GFXOPT): Replace
with
OPTION_MASK_PPC_GPOPT, OPTION_MASK_PPC_GFXOPT.
* config/rs6000/rs6000-c.cc: Update comment.
* config/rs6000/rs6000-cpus.def: Update RS6000_CPU macro calls.
* config/rs6000/rs6000.cc (rs6000_darwin_file_start): Replace
MASK_PPC_GPOPT with OPTION_MASK_PPC_GPOPT.
(rs6000_builtin_mask_names): Replace MASK_PPC_GFXOPT, MASK_POPCNTB
with OPTION_MASK_PPC_GFXOPT, OPTION_MASK_POPCNTB.
* config/rs6000/rs6000.h: (MASK_P8_VECTOR, MASK_P9_VECTOR,
MASK_P9_MISC, MASK_POPCNTB, MASK_POPCNTD, MASK_PPC_GFXOPT,
MASK_PPC_GPOPT, MASK_RECIP_PRECISION, MASK_SOFT_FLOAT,
MASK_VSX, MASK_POWER10, MASK_P10_FUSION): Delete.
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 3f7e6e380ca8..323d7c884d18 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -135,14 +135,15 @@ do {
\
#include "rs6000-cpus.def"
#undef RS6000_CPU
#undef TARGET_DEFAULT
#ifdef RS6000_BI_ARCH
-#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT \
+#define TARGET_DEFAULT (OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
#else
-#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF)
+#define TARGET_DEFAULT (OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT \
+ | OPTION_MASK_MFCRF)
#endif
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER7
#undef PROCESSOR_DEFAULT64
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index ec02022c6a9f..6a8845eb3bb7 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -365,11 +365,11 @@
/* Default target flag settings. Despite the fact that STMW/LMW
serializes, it's still a big code size win to use them. Use FSEL by
default as well. */
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT)
+#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT)
/* Darwin always uses IBM long double, never IEEE long double. */
#undef TARGET_IEEEQUAD
#define TARGET_IEEEQUAD 0
diff --git a/gcc/config/rs6000/darwin64-biarch.h
b/gcc/config/rs6000/darwin64-biarch.h
index a53e567f8b73..6515bcc8bf5a 100644
--- a/gcc/config/rs6000/darwin64-biarch.h
+++ b/gcc/config/rs6000/darwin64-biarch.h
@@ -19,11 +19,11 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \
- | OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT)
+ | OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT)
#undef DARWIN_ARCH_SPEC
#define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}"
/* Actually, there's really only 970 as an active option. */
diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index f3a81404eff3..0bec94935e2b 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -28,10 +28,10 @@ along with GCC; see the file COPYING3. If not see
| MASK_LITTLE_ENDIAN)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpower8"
#else
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT \
+#define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpower4"
#endif
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4c99afc761ae..0d13645040ff 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -382,11 +382,11 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags,
3. If either of the above two conditions apply except that the
TARGET_DEFAULT macro is defined to equal zero, and
TARGET_POWERPC64 and
a) BYTES_BIG_ENDIAN and the flag to be enabled is either
- MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
+ OPTION_MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
target), or
b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
MASK_POWERPC64 or it is one of the flags included in
ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 7d226493dc54..c3825bcccd84 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -174,92 +174,93 @@
RS6000_CPU (NAME, CPU, FLAGS)
where the arguments are the fields of struct rs6000_ptt. */
-RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
-RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
-RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | OPTION_MASK_MULHW
- | OPTION_MASK_DLMZB)
+RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT |
MASK_STRICT_ALIGN)
+RS6000_CPU ("405", PROCESSOR_PPC405, OPTION_MASK_SOFT_FLOAT
+ | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW
- | OPTION_MASK_DLMZB)
+RS6000_CPU ("440", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT
+ | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW
- | OPTION_MASK_DLMZB)
+RS6000_CPU ("464", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT
+ | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | MASK_PPC_GFXOPT
- | OPTION_MASK_MFCRF | MASK_POPCNTB
+RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
| OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
-RS6000_CPU ("476fp", PROCESSOR_PPC476,
- MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB
- | OPTION_MASK_FPRND
+RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
+ | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
-RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
-RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
-RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
-RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
-RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
-RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
-RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
-RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
+RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
+RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
+RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
+RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT)
+RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT)
+RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
-RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
-RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
-RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
-RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
+RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
+RS6000_CPU ("801", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("821", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("823", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
-RS6000_CPU ("a2", PROCESSOR_PPCA2,
- MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | OPTION_MASK_CMPB
+RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64
+ | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB
| OPTION_MASK_NO_UPDATE)
-RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
+RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
-RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
+RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT
+ | OPTION_MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
- MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
+ MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
- MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
+ MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
| OPTION_MASK_MFCRF | OPTION_MASK_ISEL)
-RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
-RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT
+RS6000_CPU ("860", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_MFCRF | MASK_POWERPC64)
-RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | MASK_PPC_GPOPT
+RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_MFCRF | MASK_POWERPC64)
-RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
-RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
+RS6000_CPU ("ec603e", PROCESSOR_PPC603, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
-RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT
+RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
-RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
- | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF)
-RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
- | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB)
-RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
- | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB
+RS6000_CPU ("power3", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT |
MASK_POWERPC64)
+RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF)
+RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB)
+RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
| OPTION_MASK_FPRND)
-RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
- | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB
+RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
| OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
- | MASK_RECIP_PRECISION)
-RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
- | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB
+ | OPTION_MASK_RECIP_PRECISION)
+RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
| OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
- | MASK_RECIP_PRECISION)
+ | OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 |
ISA_3_1_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
-RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
-RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 |
ISA_2_7_MASKS_SERVER
- | OPTION_MASK_HTM)
-RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
+ | MASK_POWERPC64)
+RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
+ | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
+RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2faac05b5045..5fd30203daac 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -20727,11 +20727,12 @@ rs6000_darwin_file_start (void)
const char *arg;
const char *name;
HOST_WIDE_INT if_set;
} mapping[] = {
{ "ppc64", "ppc64", MASK_64BIT },
- { "970", "ppc970", MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64 },
+ { "970", "ppc970", OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF \
+ | MASK_POWERPC64 },
{ "power4", "ppc970", 0 },
{ "G5", "ppc970", 0 },
{ "7450", "ppc7450", 0 },
{ "7400", "ppc7400", OPTION_MASK_ALTIVEC },
{ "G4", "ppc7400", 0 },
@@ -24060,12 +24061,12 @@ static struct rs6000_opt_mask const
rs6000_builtin_mask_names[] =
{ "crypto", OPTION_MASK_CRYPTO, false, false },
{ "htm", OPTION_MASK_HTM, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false, false },
{ "hard-float", OPTION_MASK_SOFT_FLOAT, false, false },
{ "long-double-128", OPTION_MASK_MULTIPLE, false, false },
- { "powerpc64", MASK_POWERPC64, false, false },
- { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false },
+ { "powerpc64", MASK_POWERPC64, false, false },
+ { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false },
{ "float128-hw", OPTION_MASK_FLOAT128_HW,false, false },
{ "mma", OPTION_MASK_MMA, false, false },
{ "power10", OPTION_MASK_POWER10, false, false },
};
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 4d180bd95e59..7d04556304a0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -506,23 +506,12 @@ extern int rs6000_vector_align[];
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx>
options that have not yet been replaced by their OPTION_MASK_<xxx>
equivalents are defined here. */
-#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
-#define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
-#define MASK_P9_MISC OPTION_MASK_P9_MISC
-#define MASK_POPCNTB OPTION_MASK_POPCNTB
-#define MASK_POPCNTD OPTION_MASK_POPCNTD
-#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
-#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
-#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
-#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
+
#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
-#define MASK_VSX OPTION_MASK_VSX
-#define MASK_POWER10 OPTION_MASK_POWER10
-#define MASK_P10_FUSION OPTION_MASK_P10_FUSION
#ifndef IN_LIBGCC2
#define MASK_POWERPC64 OPTION_MASK_POWERPC64
#endif
