Like base_reg_class, INDEX_REG_CLASS also does not support backend insn.
Add index_reg_class with insn argument for lra/reload usage.
gcc/ChangeLog:
* addresses.h (index_reg_class): New wrapper function like
base_reg_class.
* doc/tm.texi: Document INSN_INDEX_REG_CLASS.
* doc/tm.texi.in: Ditto.
* lra-constraints.cc (index_part_to_reg): Pass index_class.
(process_address_1): Calls index_reg_class with curr_insn and
replace INDEX_REG_CLASS with its return value index_cl.
* reload.cc (find_reloads_address): Likewise.
(find_reloads_address_1): Likewise.
Co-authored-by: Kong Lingling <lingling.k...@intel.com>
Co-authored-by: Hongtao Liu <hongtao....@intel.com>
---
gcc/addresses.h | 10 ++++++++++
gcc/doc/tm.texi | 7 +++++++
gcc/doc/tm.texi.in | 7 +++++++
gcc/lra-constraints.cc | 17 +++++++++--------
gcc/reload.cc | 4 ++--
5 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/gcc/addresses.h b/gcc/addresses.h
index 2c92927bd51..08bf39cd56c 100644
--- a/gcc/addresses.h
+++ b/gcc/addresses.h
@@ -51,6 +51,16 @@ base_reg_class (machine_mode mode ATTRIBUTE_UNUSED,
#endif
}
+inline enum reg_class
+index_reg_class (rtx_insn *insn ATTRIBUTE_UNUSED = NULL)
+{
+#ifdef INSN_INDEX_REG_CLASS
+ return INSN_INDEX_REG_CLASS (insn);
+#else
+ return INDEX_REG_CLASS;
+#endif
+}
+
/* Wrapper function to unify target macros REGNO_MODE_CODE_OK_FOR_BASE_P,
REGNO_MODE_OK_FOR_REG_BASE_P, REGNO_MODE_OK_FOR_BASE_P and
REGNO_OK_FOR_BASE_P.
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 5b1e2a11f89..c566f7a1105 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -2582,6 +2582,13 @@ address where its value is either multiplied by a scale
factor or
added to another register (as well as added to a displacement).
@end defmac
+@defmac INSN_INDEX_REG_CLASS (@var{insn})
+A C expression whose value is the register class to which a valid
+index register for a specified @var{insn} must belong. This macro is
+used when some backend insns may have limited usage of index register
+compared with other insns.
+@end defmac
+
@defmac REGNO_OK_FOR_BASE_P (@var{num})
A C expression which is nonzero if register number @var{num} is
suitable for use as a base register in operand addresses.
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index f6e63ad8871..3182d0d7c75 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -2164,6 +2164,13 @@ address where its value is either multiplied by a scale
factor or
added to another register (as well as added to a displacement).
@end defmac
+@defmac INSN_INDEX_REG_CLASS (@var{insn})
+A C expression whose value is the register class to which a valid
+index register for a specified @var{insn} must belong. This macro is
+used when some backend insns may have limited usage of index register
+compared with other insns.
+@end defmac
+
@defmac REGNO_OK_FOR_BASE_P (@var{num})
A C expression which is nonzero if register number @var{num} is
suitable for use as a base register in operand addresses.
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 6dc77af86cd..0c8e28e0194 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -3399,12 +3399,12 @@ base_plus_disp_to_reg (struct address_info *ad, rtx
disp)
/* Make reload of index part of address AD. Return the new
pseudo. */
static rtx
-index_part_to_reg (struct address_info *ad)
+index_part_to_reg (struct address_info *ad, enum reg_class index_class)
{
rtx new_reg;
new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
- INDEX_REG_CLASS, NULL, "index term");
+ index_class, NULL, "index term");
expand_mult (GET_MODE (*ad->index), *ad->index_term,
GEN_INT (get_index_scale (ad)), new_reg, 1);
return new_reg;
@@ -3659,13 +3659,14 @@ process_address_1 (int nop, bool check_only_p,
/* If INDEX_REG_CLASS is assigned to base_term already and isn't to
index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
when INDEX_REG_CLASS is a single register class. */
+ enum reg_class index_cl = index_reg_class (curr_insn);
if (ad.base_term != NULL
&& ad.index_term != NULL
- && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
+ && ira_class_hard_regs_num[index_cl] == 1
&& REG_P (*ad.base_term)
&& REG_P (*ad.index_term)
- && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
- && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
+ && in_class_p (*ad.base_term, index_cl, NULL)
+ && ! in_class_p (*ad.index_term, index_cl, NULL))
{
std::swap (ad.base, ad.index);
std::swap (ad.base_term, ad.index_term);
@@ -3689,7 +3690,7 @@ process_address_1 (int nop, bool check_only_p,
}
if (ad.index_term != NULL
&& process_addr_reg (ad.index_term, check_only_p,
- before, NULL, INDEX_REG_CLASS))
+ before, NULL, index_cl))
change_p = true;
/* Target hooks sometimes don't treat extra-constraint addresses as
@@ -3798,7 +3799,7 @@ process_address_1 (int nop, bool check_only_p,
GET_CODE (*ad.index),
curr_insn);
- lra_assert (INDEX_REG_CLASS != NO_REGS);
+ lra_assert (index_cl != NO_REGS);
new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "disp");
lra_emit_move (new_reg, *ad.disp);
*ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
@@ -3894,7 +3895,7 @@ process_address_1 (int nop, bool check_only_p,
changed pseudo on the equivalent memory and a subreg of the
pseudo onto the memory of different mode for which the scale is
prohibitted. */
- new_reg = index_part_to_reg (&ad);
+ new_reg = index_part_to_reg (&ad, index_cl);
*ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
*ad.base_term, new_reg);
}
diff --git a/gcc/reload.cc b/gcc/reload.cc
index 72f7e27af15..66b484b12fa 100644
--- a/gcc/reload.cc
+++ b/gcc/reload.cc
@@ -5114,7 +5114,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc,
rtx ad,
/* Reload the displacement into an index reg.
We assume the frame pointer or arg pointer is a base reg. */
find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
- INDEX_REG_CLASS, GET_MODE (ad), opnum,
+ index_reg_class (insn), GET_MODE (ad),
opnum,
type, ind_levels);
return 0;
}
@@ -5514,7 +5514,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t
as,
bool reloaded_inner_of_autoinc = false;
if (context == 1)
- context_reg_class = INDEX_REG_CLASS;
+ context_reg_class = index_reg_class (insn);
else
context_reg_class = base_reg_class (mode, as, outer_code, index_code,
insn);
--
2.31.1
